參數(shù)資料
型號： X80000Q32I
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Smart Power Plug Penta-Power Sequence Controller with Hot Swap
中文描述： 5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 7 X 7 MM, 0.65 MM PITCH, QFN-32
文件頁數(shù)： 23/37頁
文件大?。?/td> 695K
代理商： X80000Q32I
23
FN8148.0
March 18, 2005
Quad Voltage Monitoring
X80000 monitors 4 voltage enable inputs. When the ENi
(i=1-4) input is detected to be below the input threshold, the
output ViGOOD (i = 1 to 4) goes active. The ViGOOD signal
is asserted after a delay of 100ms. This delay can be
changed on each ViGOOD output individually with bits in
register CR3. The delay can be 100ms, 500ms, 1s and 5s.
The ViGOOD signal remains active low until ENi rises above
threshold.
Once the PWRGD signal is asserted, the power sequencing
of the DC-DC modules can commence. RESET will go active
100ms after all ViGOOD (i=1 to 4) outputs are asserted. This
delay time can be changed by setting bits in register CR2
(See Figure 32).
As shown in Figure 32, this circuit block contains four
separate voltage enable inputs, a time delay circuit, and an
output driver.
Manual Reset and Remote Shutdown
The manual reset option allows a hardware reset of either
the Gate control or the PWRGD indicator. These can be
used to recover the system in the event of an abnormal
operating condition.
The remote shutdown feature of the X80000 allows smart
power control remotely through the SMBus. The host system
can either override the control of the FET, thus turning it off,
or it can remove the override. Removing the override restarts
the power up sequence.
The X80000 has two manual reset pins: MRH (manual reset
hot side) and MRC (manual reset cold side). The MRH
signal is used as a manual reset for the GATE pin. This pin is
used to initiate Soft Reinsert. When MRH is pulled LOW the
GATE pin will be pulled LOW. It also clears the Remote
Shutdown Register (RSR) and the FAR signal. When the
MRH pin goes HIGH, it removes the override signal and the
Control
Remote
& Fault
Registers
EEPROM
2Kbits
RESET Logic
t
SPOR
Delay
SPOR
MRC
SDA
V
DD
Drain Sense
& Power
Good Logic
Enable
Logic
RESET
PWRGD
ViGOOD
i = 1 to 4
μ
P
B
SCL
V
EE
FIGURE 31. POWER ON/SYSTEM RESET AND DELAY
(BLOCK DIAGRAM)
TABLE 12. ViGOOD OUTPUT TIME DELAY OPTIONS
TiD1
TiD0
t
DELAYi
0
0
100ms
0
1
500ms
1
0
1 secs
1
1
5 secs
where i is the ith voltage enable (i = 1 to 4).
EN1
EN2
EN3
EN4
V4GOOD
V3GOOD
V2GOOD
V1GOOD
V
EE
Divider
Reset
4
OSC
0.5s
5s
0.1s
4
delay1
delay2
delay3
delay4
Delay circuit
repeated 4 times
V
RGO
Control Register
SMBus Interface
Fault Detection Register
FIGURE 32. VOLTAGE ENABLE CONTROL AND VGOOD OUTPUTS
X80000, X80001
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