參數(shù)資料
型號(hào)： X80000Q32I
廠商： INTERSIL CORP
元件分類(lèi)： 電源管理
英文描述： Smart Power Plug Penta-Power Sequence Controller with Hot Swap
中文描述： 5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 7 X 7 MM, 0.65 MM PITCH, QFN-32
文件頁(yè)數(shù)： 22/37頁(yè)
文件大?。?/td> 695K
代理商： X80000Q32I
22
FN8148.0
March 18, 2005
external pins, IGQ1 and IGQ0, that allow the system to
switch to different GATE current on-the-fly with pre-selected
I
GATE
currents.
The IGQ1 and IGQ0 pins can be used to select from one of
four set values.
Typically, the delay from IGQ1 and IGQ0 selection to a
change in the GATE pin current is less than 1
μ
second.
Drain Sense and Power Good Indicator
The X80000 provides a drain sense and power good
indicator circuit. The PWRGD signal asserts LOW when
there is no overvoltage, no undervoltage, and no overcurrent
condition, the Gate voltage exceeds VDD-1V, and the
voltage at the DRAIN pin is less V
EE
+V
DRAIN
.
As shown in Figure 30, this circuit block contains a drain
sense voltage trip point (
V
DRAIN
) and a gate voltage trip
point (
V
GATE
), two comparators, and internal voltage
references. These provide both a drain sense and a gate
sense circuit to determine the whether the FET has turned
on as requested. If so, the power good indicator (PWRGD)
goes active.
The drain sense circuit checks the DRAIN pin. If the voltage
on this pin is greater that 1V above V
EE
, then a fault
condition exists.
The gate sense circuit checks the GATE pin. If the voltage
on this pin is less than V
EE
- 1V, then a fault condition exists.
The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:
there is no overvoltage or no undervoltage condition, (i.e.
undervoltage < V
EE
< overvoltage.)
There is no overcurrent condition (i.e. V
EE
- V
SENSE
<
V
OC
.)
The FET is turned on (i.e. V
DRAIN
< V
EE
+ 1V and V
GATE
> V
DD
- 1V).
Power On Reset and System Reset With Delay
Application of power to the X80000 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, provides several benefits.
It prevents the system microprocessor from starting to
operate with insufficient voltage.
It prevents the processor from operating prior to
stabilization of the oscillator.
It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.
The SPOR/RESET circuit is activated when all voltages are
within specified ranges and the following time-out conditions
are met: PWRGD and V1GOOD, V2GOOD, V3GOOD, and
V4GOOD. The SPOR/RESET circuit will then wait 100ms
and assert the RESET pin. The SPOR delay may be
changed by setting the TPOR bits in register CR2. The delay
can be set to 100 ms, 500 ms, 1 second, or 5 seconds.
IGQ1
PIN
IGQ0
PIN
CONTENTS
0
0
Defaults to gate current set by IG3:IG0 bits
0
1
Gate Current is 10
μ
A
1
0
Gate Current is 70
μ
A
1
1
Gate Current is 150
μ
A
TABLE 11. SPOR RESET DELAY OPTIONS
TPOR1
TPOR0
t
SPOR
DELAY BEFORE RESET
ASSERTION
0
0
100 miliseconds (default)
0
1
500 miliseconds
1
0
1 second
1
1
5 seconds
(Factory
Programmable)
SENSE
V
EE
R
SENSE
LOAD
GATE
DRAIN
100K
-48V
SDA
SCL
SMBus
PWRGD
+
–
1V
V
EE
Control/Status
Registers
Power
Good
Logic
V
DRAIN
+
–
VDD-1V
V
GATE
FIGURE 30. DRAIN SENSE AND POWER GOOD INDICATOR
X80000, X80001
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