參數(shù)資料
型號： X40231
英文描述： Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
中文描述： 綜合系統(tǒng)管理IC三電壓監(jiān)測器，葡萄牙，2千比特的EEPROM內(nèi)存，單/雙副處長（帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器）
文件頁數(shù)： 18/39頁
文件大?。?/td> 215K
代理商： X40231
X4023x
– Preliminary Information
Characteristics subject to change without notice.
18 of 39
REV 1.0.4 7/12/01
www.xicor.com
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X4023x con-
tinues to output a Data Byte for each ACKNOWLEDGE
received. The master terminates the read operation by
not responding with an ACKNOWLEDGE and instead
issuing a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through the entire memory contents to be serially read
during one operation. At the end of the address space
the counter “rolls over” to address 00h and the device
continues to output data for each ACKNOWLEDGE
received (Refer to Figure 16).
CONTROL AND STATUS REGISTER
The Control and Status (CR) Register provides the
user with a mechanism for changing and reading the
status of various parameters of the X4023x (See Fig-
ure 17).
The CR register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CR register
retain their stored values even when V
down, then powered back up. The volatile bits however,
will always power up to a known logic state “0” (irre-
spective of their value at power down).
CC
is powered
A detailed description of the function of each of the CR
register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X4023x device. This bit must first be enabled
before ANY write operation (to DCPs, EEPROM mem-
ory array, or the CR register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CR register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CR register. Once enabled, the
WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CR register) or until the
X4023x powers down, and then up again.
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition
is executed in the CR Write command sequence (See
Figure 18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CR) Register Write Enable
status of the X4023x. Therefore, in order to write to any
of the bits of the CR Register (except WEL), the RWEL
bit must first be set to “1”. The RWEL bit is a volatile bit
that powers up in the disabled, LOW (“0”) state.
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See "CR
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of the CR
register has been completed (See Figure 18).
—When the X4023x is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used
to:
—Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper posi-
tion”).
Bit(s)
Description
WEL
Write Enable Latch bit
RWEL
Register Write Enable Latch bit
V2FS
V2MON Output Flag Status
V3FS
V3MON Output Flag Status
BL1 - BL0
Sets the Block Lock partition
PUP1 - PUP0
Sets the Power On Reset time
PUP1
WEL
PUP0
CS5
CS6
CS7
CS4
CS3
CS2
CS1
CS0
V3FS
V2FS
BL0
BL1
RWEL
Figure 17. CR Register Format
NV
NV
NV
NV
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X40231S163-A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40231S163-B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40231S165-A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40231S165-B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
X40231S167-A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
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