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參數(shù)資料
| 型號(hào)： | X40231 |
| 英文描述： | Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器) |
| 中文描述： | 綜合系統(tǒng)管理IC三電壓監(jiān)測器，葡萄牙，2千比特的EEPROM內(nèi)存，單/雙副處長（帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器） |
| 文件頁數(shù)： | 17/39頁 |
| 文件大?。?/td> | 215K |
| 代理商： | X40231 |
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X4023x
– Preliminary Information
Characteristics subject to change without notice.
17 of 39
REV 1.0.4 7/12/01
www.xicor.com
the Device Type Identifier 1010111 or 1010010). Imme-
diately after an operation to a DCP or CR Register is
performed, only a “Random EEPROM Read” is avail-
able. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or
“Sequential EEPROM Read” is once again available
(assuming that no access to a DCP or CR Register
occur in the interim).
Random EEPROM Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the START condition and the Slave
Address Byte, receives an ACKNOWLEDGE, then
issues an Address Byte. This “dummy” Write operation
sets the address pointer to the address from which to
begin the random EEPROM read operation.
After the X4023x acknowledges the receipt of the
Address Byte, the master immediately issues another
START condition and the Slave Address Byte with the
R/W bit set to one. This is followed by an ACKNOWL-
EDGE from the X4023x and then by the eight bit word.
The master terminates the read operation by not
responding with an ACKNOWLEDGE and instead issu-
ing a STOP condition (Refer to Figure 15).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In
this case, the device sets the address pointer to that of
the Address Byte, and then goes into standby mode
after the STOP bit. All bus activity will be ignored until
another START is detected.
Slave
Address
Address Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 15. Random EEPROM Address Read Sequence
0 1 0 0 0 0
1
1 0 1 0 0 0 0
WRITE Operation
“Dummy” Write
READ Operation
0
1
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
Figure 16. Sequential EEPROM Read Sequence
0 0 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40231S163-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| X40231S163-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| X40231S165-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| X40231S165-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
| X40231S167-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
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