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參數(shù)資料
| 型號： | WV3EG232M64STSU335D4SG |
| 英文描述： | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| 中文描述： | 512MB的- 2x32Mx64 DDR SDRAM內(nèi)存緩沖 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 195K |
| 代理商： | WV3EG232M64STSU335D4SG |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WV3EG232M64STSU-D4
September 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
I
DD
SPECIFICATIONS AND TEST CONDITIONS
-40°C ≤ T
A
≤ 85°C, V
CC
= V
CCQ
= 2.5V ±0.2V
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5 Max
840
Unit
Operating current:
I
DD0*
One device bank active; Active-Precharge; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
; DQ,DM
and DQS inputs change once per clock cycle; Address and control inputs
change once every two clock cycles
One device bank; Active-Read-Precharge; BL=4; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
;
I
OUT
= 0mA; Address and control inputs change once per clock cycle
All device banks are idle; Power-down mode; t
CK
= t
CK(MIN)
; CKE=LOW
mA
Operating current
I
DD1*
1120
mA
Percharge power-
down standby current
Idle standby current
I
DD2P**
40
mA
I
DD2F**
CS# = HIGH; All device banks are idle; t
CK
= t
CK(MIN)
; CKE=HIGH; Address
and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM
One device bank active; Power-down mode; t
CK
= t
CK(MIN)
; CKE=LOW
240
mA
Active power-down
standby current
Active standby
current
I
DD3P**
240
mA
I
DD3N**
CS# = HIGH; CKE=HIGH; One device bank active; t
RC
= t
RAS(MAX)
; t
CK
=
t
CK(MIN)
; DQ, DM and DQS inputs change twice per clock cycle; Address and
other control inputs changing once per clock cycle
Burst = 2; Reads; Continuos burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; I
OUT
= 0mA
Burst = 2; Writes; Continuos burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; DQ, DM and
DQS inputs change twice per clock cycle
t
RC
=t
RFC(MIN)
CKE < 0.2V
Four device bank interleaving Reads Burst=4 with auto precharge; t
CK
=
t
CK(MIN)
; Address and control inputs change only during Active READ, or
WRITE commands
360
mA
Operating current
I
DD4R*
1360
mA
Operating current
I
DD4W*
1480
mA
Auto refresh current
Self refresh current
Orerating current
I
DD5**
I
DD6**
I
DD7A*
1640
40
3040
mA
mA
mA
NOTE:
I
DD
specification is based on
SAMSUNG
components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in I
DD2P
(CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WV3EG232M64STSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| WV3EG264M64EFSU262D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU262D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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