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參數(shù)資料
| 型號(hào)： | WSE128K16-42G2TMA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, CQMA68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 14/15頁(yè) |
| 文件大小： | 635K |
| 代理商： | WSE128K16-42G2TMA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)
WSE128K16-XXX
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
March 2005
Rev. 3
FIGURE 9 – EEPROM READ WAVEFORMS
EEPROM READ
The WSE128K16-XXX EEPROM stores data at the
memory location determined by the address pins. When
ECS# and OE# are low and EWE# is high, this data is
present on the outputs. When ECS# and OE# are high,
the outputs are in a high impedance state. This two line
control prevents bus contention.
Note: OE# may be delayed up to tACS - tOE after the falling edge of ECS# without impact on tOE or by tACC - tOE after an address change without impact on tACC.
EEPROM AC READ CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Read Cycle Parameter
Symbol
-120
-150
-300
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
120
150
300
ns
Address Access Time
tACC
120
150
300
ns
Chip Select Access Time
tACS
120
150
300
ns
Output Hold from Add. Change, OE# or ECS#
tOH
000
ns
Output Enable to Output Valid
tOE
050055085
ns
Chip Select or OE# to High Z Output
tDF
70
ns
tOH
ADDRESS
ECS#1-2
OE#
EEPROM
DATA
OUTPUT
tDF
tACC
tRC
tOE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
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