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參數(shù)資料
| 型號： | W971GG6IB-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 |
| 文件頁數(shù)： | 4/86頁 |
| 文件大?。?/td> | 1360K |
| 代理商： | W971GG6IB-25 |
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W971GG6IB
Publication Release Date: Oct. 23, 2009
- 12 -
Revision A02
7.2.2.2
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA1
BA0 A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
OCD program
BT
Rtt
Address Field
Extended Mode Register (1)
BA1 BA0
MRS mode
0
1
11
MR
EMR (1)
EMR (2)
EMR (3)
A6
A2
0
1
11
WR
Additive Latency
Qoff
0*
1
DQS
Rtt O.I.C DLL
Rtt (nominal)
ODT Disabled
75 ohm
150 ohm
50 ohm*2
0
A0
1
DLL Enable
Enable
Disable
OCD Calibration Program
OCD calibration mode exit; matain setting
Adjust mode*3
OCD Calibration default*4
Drive (1)
Drive (0)
A9
A8
A7
1
00
0
11
1
00
0
Driver impedance adjustment
A12
1
0
Output buffer enabled
Qoff (Optional)*5
Output buffer disabled
A10
1
0
DQS
Enable
Disable
A10
(DQS Enable)
0 (Enable)
1 (Disable)
Strobe Function Matrix
DQS
Hi-z
Output driver
impedance control
Reduced
Normal
A1
0
1
A5
0
1
A4
0
1
0
1
A3
0
1
0
1
0
1
0
Latency
0
3
4
Reserved
1
2
Output Driver Impedance Control
Driver
size
100%
60%
Additive Latency
5
6
DDR2-
/6
67/
80
0(
-3/
-25
)
DDR2-
1
06
6
(
-18)
BA2
0
Notes:
1. A11 default is “0 “ RDQS disabled.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
detailed information.
5. Output disabled - DQs, LDQS, LDQS , UDQS, UDQS . This feature is used in conjunction with DIMM IDD measurements
when IDDQ is not desired to be included.
Figure 3—EMR (1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W9751G6JB-25A | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| W9751G8JB-18 | DDR DRAM, PBGA84 |
| W9812G21H-6I | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| W9812G6JH-6 | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W971GG6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM |
| W971GG6JB-18 | 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS |
| W971GG6JB-25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA |
| W971GG6JB25I | 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| W971GG6JB-25I | 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY |
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