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參數(shù)資料
| 型號： | W948D6FBHX6E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 29/60頁 |
| 文件大?。?/td> | 1147K |
| 代理商： | W948D6FBHX6E |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 35 -
Revision A01-003
7.6.3 Write Burst (min. and max. tDQSS)
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the
WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state
of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on
DQS following the last data-in element is called the write post-amble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a
relatively wide range - from 75% to 125% of a clock cycle. Following figure shows the two extremes of tDQSS for a
burst of 4, upon completion of a burst, assuming no other commands have been initiated, the DQs will remain high-Z
and any additional input data will be ignored.
BA,Col b
WRITE
NOP
CK
Command
Address
1) DI b = Data In to column b.
2) 3 subsequent elements of Data In are applied i nthe programmed order following DI b.
3) A non-interrupted burst of 4 is shown.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
NOP
= Don't Care
DQS
DQ
DM
DQS
DQ
DM
tDQSSmin
tDQSSmax
7.6.4 Write to Write
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive
edge of the clock following the previous WRITE command.
The first data-in element from the new burst is applied after either the last element of a completed burst or the last
desired data element of a longer burst which is being truncated. The new WRITE command should be issued X
cycles after the first WRITE command, where X equals the number of desired data-in element pairs.
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| WF512K32NA-120HSM5 | 512K X 32 FLASH 5V PROM MODULE, 120 ns, CHIP66 |
| WS128K32-70CJC | 512K X 8 MULTI DEVICE SRAM MODULE, 70 ns, CQCC68 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W948D6FBHX6ETR | 制造商:Winbond Electronics Corp 功能描述:256M MDDR, X16, 166MHZ, 65NM |
| W948D6FBHX6G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:256Mb Mobile LPDDR |
| W949D2CB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D2CBJX5E | 功能描述:IC LPDDR SDRAM 512MBIT 90VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
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