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參數(shù)資料
| 型號： | W3E32M64S-266SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM, 0.75 ns, PBGA208 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 648K |
| 代理商： | W3E32M64S-266SBC |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E32M64S-XSBX
January 2008
Rev. 6
TABLE 1 – BURST DEFINITION
NOTES:
1.
For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2.
For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3.
For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
FIGURE 3 MODE REGISTER DEFINITION
M3 = 0
2
4
8
Reserved
M3 = 1
2
4
8
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
Valid
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Operating Mode
A10
A11
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
0*
BA0
BA1
Reserved
3
M9
M10
M11
0
10
0
--
-
A12
M12
0
-
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3E32M64S-266SBM | 制造商:White Electronic Designs 功能描述:DRAM Module DDR SDRAM 256Mbyte 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-333BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-333BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-333BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
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