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參數(shù)資料
| 型號(hào)： | W134SHT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DIFF DIRECT RAMBUS 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Direct Rambus™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W134
........................ Document #: 38-07426 Rev. *C Page 7 of 11
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During tCLKON, the clock output is not
specified and can have glitches. For tCLKON < t < tCLKSETL, the
clock output is enabled and must be glitch-free. For
t>tCLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of the Device Characteristics table. The
outputs are in a high-impedance state during the Clk Stop
mode.
E
Clk Stop
Normal
tCLKON
10 ns
Time from StopB until Clk/ClkB provides glitch-free
clock edges.
E
Clk Stop
Normal
tCLKSETL 20 cycles Time from StopB to Clk/ClkB output settled to within 50
ps of the phase before CLK/CLKB was disabled.
F
Normal
Clk Stop
tCLKOFF
5 ns
Time from StopB to Clk/ClkB output disabled.
LTest
Normal
tCTL
3 ms
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
N
Normal
Test
tCTL
3 ms
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
B,D
Normal or Clk Stop
Power-down tPOWERDN
1 ms
Time from PwrDnB to the device in Power-down.
Table 8. State Transition Latency Specifications (continued)
Transition
From
To
Transition Latency
Description
Parameter
Max.
Table 9. Distributed Loop Lock Time Specification
Parameter
Description
Min.
Max.
Unit
tDISTLOCK Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
PclkM falls within the tERR,PD spec in Table .
5ms
Table 10.Supply and Reference Current Specification
Parameter
Description
Min.
Max.
Unit
IPOWERDOWN
“Supply” current in Power-down state (PwrDnB 1 = 0)
–
250
A
ICLKSTOP
“Supply” current in Clk Stop state (StopB = 0)
–
65
mA
INORMAL
“Supply” current in Normal state (StopB = 1, PwrDnB = 1)
–
100
mA
IREF,PWDN
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
–
50
A
IREF,NORM
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)
–
2
mA
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