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參數(shù)資料
| 型號： | W134SHT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DIFF DIRECT RAMBUS 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Direct Rambus™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W134
........................ Document #: 38-07426 Rev. *C Page 9 of 11
Notes:
9. Output Jitter spec measured at tCYCLE = 2.5 ns.
10. Output Jitter Spec measured at tCYCLE = 3.75 ns.
11. VCOS = VOH–VOL.
12. rOUT = DVO/ D IO. This is defined at the output pins.
Device Characteristics
Parameter
Description
Min.
Max.
Unit
tCYCLE
Clock Cycle Time
2.5
3.75
ns
tJ
Cycle-to-Cycle Jitter at Clk/ClkB[9]
–60
ps
Total Jitter over 2, 3, or 4 Clock Cycles[9]
–
100
ps
266-MHz Cycle-to-Cycle Jitter[10]
–
100
ps
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles[10]
–
160
ps
tSTEP
Phase Aligner Phase Step Size (at Clk/ClkB)
1
–
ps
tERR,PD
Phase Detector Phase Error for Distributed Loop Measured at
PclkM-SynclkN (rising edges) (does not include clock jitter)
–100
100
ps
tERR,SSC
PLL Output Phase Error when Tracking SSC
–100
100
ps
VX,STOP
Output Voltage during Clk Stop (StopB=0)
1.1
2.0
V
VX
Differential Output Crossing-Point Voltage
1.3
1.8
V
VCOS
Output Voltage Swing (p-p single-ended)[11]
0.4
0.6
V
VOH
Output High Voltage
–
2.0
V
VOL
Output Low voltage
1.0
–
V
rOUT
Output Dynamic Resistance (at pins)[12]
12
50
IOZ
Output Current during Hi-Z (S0 = 0, S1 = 1)
–
50
A
IOZ,STOP
Output Current during Clk Stop (StopB = 0)
–
500
A
DC
Output Duty Cycle over 10,000 Cycles
40
60
%tCYCLE
tDC,ERR
Output Cycle-to-Cycle Duty Cycle Error
–
50
ps
tR,tF
Output Rise and Fall Times (measured at 20%–80% of output voltage)
250
500
ps
tCR,CF
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%–80%)
–
100
ps
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