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參數(shù)資料
| 型號： | W134SHT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 0K |
| 描述： | IC CLK DIFF DIRECT RAMBUS 24QSOP |
| 標準包裝： | 1,000 |
| 系列： | Direct Rambus™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W134
........................ Document #: 38-07426 Rev. *C Page 2 of 11
Pin Definitions
Pin Name
No.
Type
Description
REFCLK
2
I
Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
PCLKM
6
I
Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
SYNCLKN
7
I
Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
STOPB
11
I
Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
PWRDNB
12
I
Active LOW Power-down. When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
MULT 0:1
15, 14
I
PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
CLK, CLKB
20, 18
O
Complementary Output Clock. Differential Rambus Channel clock outputs.
S0, S1
24, 23
I
Mode Control Input. These inputs control the operating mode of the W134M/W134S.
NC
19
–
No Connect
VDDIR
1
RefV Reference for REFCLK. Voltage reference for input reference clock.
VDDIPD
10
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
VDD
3, 9, 16, 22
P
Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
GND
4, 5, 8, 13, 17,
21
G
Ground Connection. Connect all ground pins to the common system ground plane.
MULT1
0
1
0
MULT0
0
1
W134M
PLL/REFCLK
4.5
6
8
5.333
W134S
PLL/REFCLK
4
6
8
5.333
S1
0
1
0
1
S0
0
1
MODE
Normal
Output Enable Test
Bypass
Test
W134M/W134S
Refclk
W133
PLL
Phase
Align
D
4
DLL
RAC
RMC
M
N
Gear
Ratio
Logic
Pclk
Busclk
Synclk
Pc
lk
/M
S
y
n
c
lk
/N
W158
W159
W161
W167
Figure 1. DDLL System Architecture
CY2210
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