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參數(shù)資料
| 型號： | VV5410C036 |
| 廠商： | 意法半導體 |
| 英文描述： | Mono and Colour Digital Video CMOS Image Sensors |
| 中文描述： | 莫諾和數(shù)字視頻彩色CMOS圖像傳感器 |
| 文件頁數(shù)： | 22/105頁 |
| 文件大?。?/td> | 489K |
| 代理商： | VV5410C036 |
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VV5410 & VV6410
Exposure Control
cd5410-6410f-3-0.fm
Commercial in confidence
22/105
note: The relationship between the programmed gain value as written to register[36] and the igain (current gain) and
cgain (capacitive gain) is as follows:
igain
If mode_select[24], bit 1 is set then igain[3:0] is the inverse of gain[3:0], i.e. if gain[3:0] = 6, igain[3:0] = 9.
If mode_select[24], bit 1 is reset then igain[3:0] is the inverse of the mirror of gain[3:0], i.e. bit 3 of igain is the inverse of bit 0 of
gain, i.e. gain = 4 and igain = 13.
cgain
cgain is a 6 bit value therefore we have to pad the 4 bits of the gain register. In 10bit modes cgain[1:0] is fixed at 2’b11 and
cgain[5:2] is set to gain[7:4]. In the 9bit modes cgain[1:0] is also set to 2’b11, however cgain[5:2] is set to gain[7:4] divided by 2,
thus gain[7:4] = 4’b1111 gives cgain[5:0] = 6’b011111.
6.2.1
To ensure optimum sensor performance it is recommended that the igain setting, controlled by the ls nibble of serial
register[36
10
], be limited to 12.
Recommended Gain Settings
6.3
Although the clock divisor register is an 8 bit register the user only has write access to the lower 4 bits as described above. The
upper 4 bits of the register are altered automatically when the video mode is changed by writing to Setup0[16] register. The upper
4 bits are pre-programmed as follows:
Clock Division
10bit ADC mode
9bit ADC mode
gain[7:0]
igain[3:0]
cgain[5:0]
Overall
Gain
gain[7:0]
igain[3:0]
cgain[5:0]
8’hfe
1 (0001
2
)
63
8.000
8’hfe
1 (0001
2
)
31
8.000
8’hfd
2 (0010
2
)
63
5.333
8’hfd
2 (0010
2
)
31
5.333
8’fc
3 (0011
2
)
63
4.000
8’fc
3 (0011
2
)
31
4.000
8’hfb
4 (0100
2
)
63
3.200
8’hfb
4 (0100
2
)
31
3.200
8’hfa
5 (0101
2
)
63
2.667
8’hfa
5 (0101
2
)
31
2.667
8’hf9
6 (0110
2
)
63
2.2857
8’hf9
6 (0110
2
)
31
2.2857
8’hf8
7 (0111
2
)
63
2.0000
8’hf8
7 (0111
2
)
31
2.0000
8’hf7
8 (1000
2
)
63
1.7778
8’hf7
8 (1000
2
)
31
1.7778
8’hf6
9 (1001
2
)
63
1.6000
8’hf6
9 (1001
2
)
31
1.6000
8’hf5
10 (1010
2
)
63
1.4545
8’hf5
10 (1010
2
)
31
1.4545
8’hf4
11 (1011
2
)
63
1.3333
8’hf4
11 (1011
2
)
31
1.3333
8’hf3
12 (1100
2
)
63
1.2308
8’hf3
12 (1100
2
)
31
1.2308
8’hf2
13 (1101
2
)
63
1.1429
8’hf2
13 (1101
2
)
31
1.1429
8’hf1
14 (1110
2
)
63
1.0667
8’hf1
14 (1110
2
)
31
1.0667
8’hf0
15 (1111
2
)
63
1.0000
8’hf0
15 (1111
2
)
31
1.0000
Table 7 : Analogue Gain Settings
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