參數(shù)資料
型號: VSC870TX
廠商: VITESSE SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: High Performance Serial Backplane Transceiver
中文描述: DUAL LINE TRANSCEIVER, PBGA192
封裝: BGA-192
文件頁數(shù): 33/40頁
文件大?。?/td> 511K
代理商: VSC870TX
VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
G52190-0, Rev 4.1
01/05/01
Page 33
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Table 1: LVDS and TTL Outputs
Figure 17: Transmit Data Input Timing Diagram
Table 2: Transmit Data Input Timing Table
NOTE: Duty cycle for WCLK and WSOUT is 50% +/- 10% worst case.
During initialization, the WSOUT minimum pulse width can be reduced by an additional 1nS.
Parameters
Description
Min
Typ
Max
Units
Conditions
T
R,TTL
T
F,TTL
T
R,LVDS
T
F,LVDS
TTL Output Rise Time
TTL Output Fall Time
LVDS Output Rise Time
LVDS Output Fall Time
2.5
2.5
ns
ns
ps
ps
10-90% @ 50pF
10-90% @ 50pF
20-80%
20-80%
100
100
Parameter
Description
Min
Typ
Max
Units
T
WCLK
T
INSU1
T
INSU1
T
INSU1
T
INSU1
T
INH1
T
WSOUT
T
INSU2
T
INSU2
Word clock period
TXIN[31:0] setup time with respect to WCLK
TXTYP[1:0] setup time with respect to WCLK
TXEN setup time with respect to WCLK
ABORT, RTR setup time with respect to WCLK
Data hold time with respect to WCLK
Word Synch Output clock period
TXIN[31:0] setup time with respect to WSIN
TXTYP[1:0] setup time with respect to WSIN
DLYEN/CCKIN, TXEN setup time with respect to
WSIN
ABORT, RTR setup time with respect to WSIN
Data hold time with respect to WSIN
Delay time from WSIN to WCLK
16.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
6.0
7.0
8.5
0.0
16.0
2.0
2.0
T
INSU2
2.5
ns
T
INSU2
T
INH2
T
DEL
4.5
2.0
1.6
ns
ns
ns
5.5
T
WSOUT
T
INSU1
T
INH1
WCLK
TXIN[31:0], TXTYP[1:0],
DLYEN/CCKIN, TXEN, ABORT RTR
T
WCLK
WSIN
T
INSU2
T
INH2
T
DEL
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