- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359432 > VSC870TX (VITESSE SEMICONDUCTOR CORP) High Performance Serial Backplane Transceiver PDF資料下載
參數(shù)資料
| 型號： | VSC870TX |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Performance Serial Backplane Transceiver |
| 中文描述： | DUAL LINE TRANSCEIVER, PBGA192 |
| 封裝： | BGA-192 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 511K |
| 代理商： | VSC870TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
Page 18
G52190-0, Rev 4.1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
cards. During Early Arbitration, the early CRQ is camped on in the switch and is arbitrated every cycle until another
IDLE or CRQ word arrives. This means it is at the highest priority level regardless of CT counter. If the connection
has not been granted at this point, CRQ sequences begin based on the MD and CT bits in the CRQ word as described
below.
2.3.3 Delay Enable Signal
If the signal DLYEN/CCKIN is set HIGH, a pre-programmed delay will occur between the time an ACK is
received from the switch chip, and the signal REN (read enable) goes HIGH to start reading data at the parallel
interface. Users can set this number to any value between 0 & 15 by using the 4 bits described in the command word
in section 1.2.3. The default value is 6 word clock cycles. If the signal DLYEN/CCKIN is set LOW, the value is 0 no
matter what value was programmed in. If the input buffer system is a single queue FIFO, after receiving ACK, the
FIFO can send data out at once. In this case, the DLYEN/CCKIN signal can be set LOW to force REN HIGH right
after receiving ACK signal. If the input buffer system is designed with multiple data queues, users can use the Multi
Queue mode to improve throughput. In this mode, after the ACK signal is sent back to the FIFO, the transceiver takes
4 more cycles to send 4 bits of information containing the granted queue ID. The FIFO might take some extra time to
process this information before it can send out data to the new destination. To account for this extra latency, The
DLYEN/CCKIN signal can be set HIGH to force the transceiver to wait for 6 more cycles after receiving ACK before
it can sends the data for the next packet. This 6 cycles of delay is set by default in the transceiver after reset. If the
default value of 6 cycles is used, the value for early arbitration should be set to 9+6=14.
2.3.4 Out of Synch Conditions
There are two out of synch conditions that can occur during packet mode operation. The serial link from the
transmitting port card can go out of synch, or the serial link to the receiving port card can go out of synch. If the serial
link on the transmitting side goes out of synch, the switch will send alignment patterns to the transceiver, and the
transmitting port card is signaled on the OOS pin of the transceiver. When this happens, there is a chance that the
receiving port card will receive only a partial packet. In this case, the CRQ word with BRK set HIGH will not be
received; therefore, the receiving port card knows it did not receive the end of packet properly. If the serial link on the
receiving side goes out of synch, the receiving transceiver will set the RXOK and TXOK pins high, and the OOS pin
will also go high to indicate that the transceiver is in the link initialization process. The transmitting port card is not
signaled for this condition through the switch chip. The user must make this condition known to the transmitting port
card through some other means. If one of the output ports on the switch chip is in the out of synch state, any request
for connection to this output will always be granted. In addition, no flow control back pressure will be applied from
this output. This is to make sure multicast connections will not get permanently locked up, but packets could be lost
in this case.
2.3.5 Unicast / Multicast Camp-on with Priority Mode (MD[1:0] = 00)
In this mode, after the transceiver is loaded with a single CRQ at the parallel interface, it will send one CRQ
word to the switch and wait for the ACK. During early arbitration, the switch will store this CRQ and arbitrate until
all the outputs requested are granted. During this time, the transceiver can send more data words for the end of the last
packet (the number of data words sent must be less than or equal to D). The value for D can also be set to zero. If the
transceiver detects the header word for the next packet at the parallel interface before receiving an ACK (see figure
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VSC872 | 80 Gb/s Intelligent Switch Fabric |
| VSC874 | 10 Gbps Queue Manager with Integrated SPI4.2 Interface |
| VSC880 | High Performance 16x16 Serial Crosspoint Switch |
| VSC9110 | Target Specification |
| VSC9115 | 2.5 Gb/s Multi-Service SONET/SDH Mapper Device with Virtual Concatenation |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC872 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:80 Gb/s Intelligent Switch Fabric |
| VSC872TV01 | 制造商:Vitesse Semiconductor Corporation 功能描述: |
| VSC874 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:10 Gbps Queue Manager with Integrated SPI4.2 Interface |
| VSC880 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:High Performance 16x16 Serial Crosspoint Switch |
| VSC880TY | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:High Performance 16x16 Serial Crosspoint Switch |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。