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參數(shù)資料
| 型號： | VSC7216UC-01 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Multi-Gigabit Interconnect Chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, BGA-256 |
| 文件頁數(shù)： | 9/38頁 |
| 文件大小： | 561K |
| 代理商： | VSC7216UC-01 |
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Preliminary Datasheet
VSC7216-01
Multi-Gigabit Interconnect Chip
VITESSE
G52352-0, Rev 3.2
05/05/01
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
10B/8B Decoder
The 10-bit character from the deserializer is decoded in the 10B/8B decoder, which outputs the 8B data byte
and three bits of status information. If the 10-bit character does not match any valid value, an Out-of-Band Error
is generated which is output on the receiver status bus. Similarly, if the running disparity of the character does
not match the expected value, a Disparity Error is generated. The decoder also reports when a K-character is
received, and distinguishes the K28.5 (IDLE) character from other K-characters. This status information is
combined with LOS State Machine status and FIFO error status, to produce the prioritized per-character link
status output information (see Table 8).
Elastic Buffer and Channel De-Skewing
An elastic buffer is included in each of the four receive channels. Decoded data and status information is
written into these buffers on each channel
’
s recovered clock, and is read on the selected output clock. In
addition to allowing decoded data to easily cross from a channel
’
s recovered clock domain to its output clock
domain, the elastic buffers facilitate channel alignment (the reconstruction of a multi-byte word as presented to
the transmitting devices), and they facilitate rate matching via IDLE character insertion/deletion when the
channel
’
s recovered clock is not frequency-locked to its output clock.
There are three conditions under which a receive channel
’
s elastic buffer is recentered: the RESETN input,
when asserted, recenters the read/write pointers in each elasticity buffer; whenever a
“
Comma
”
character is
received which changes the receive character
’
s framing boundary, the elasticity buffer is recentered; and lastly,
it is also recentered whenever the receiver detects the synchronization point in the Word Sync Sequence. All
three of these events are associated with chip initialization or link initialization and would not occur during
normal data transfer. Note that recentering can result in the loss or duplication of decoded character data and
status information.
When a condition change transmit timing (e.g., phase shifts in TBC) or shifts phase/alignment into the
receiver, the user should initial a Word Sync Event to recenter all elasticity buffers. Otherwise, data corruption
could occur.
The VSC7216-01 presents recovered data on Rn(7:0) and status on IDLEn, KCHn and ERRn. These
outputs are timed either to each channel
’
s own recovered clock (RCLKn/RCLKNn), to Channel A
’
s recovered
clock (RCLKA/RCLKNA), or to REFCLK. The output timing reference is selected by RMODE(1:0) (see Table
6). The transmitter input skew buffer error outputs TBERRn and the analog signal detect outputs PSDETn and
RSDETn are also synchronized to the selected output timing reference. There are two choices for REFCLK-
based timing, which differ in the positioning of the data valid window associated with the output signals timed
to REFCLK: when RMODE(1:0)=00 REFCLK is approximately centered in the output data valid window as in
the VSC7214 and when RMODE(1:0)=01 REFCLK slightly leads the data valid window so that output data
appears to have a more typical
“
Clock-to-Q
”
timing relationship to REFCLK.
Table 6: Receive Interface Output Timing Mode
RMODE(1:0)
Output Timing Reference
0 0
REFCLK (centered)
0 1
REFCLK (leading)
1 0
RCLKA/RCLKNA
1 1
RCLKn/RCLKNn
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