參數(shù)資料
型號(hào)： VSC7216UC-01
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Multi-Gigabit Interconnect Chip
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.27 MM PITCH, BGA-256
文件頁數(shù)： 17/38頁
文件大小： 561K
代理商： VSC7216UC-01
Preliminary Datasheet
VSC7216-01
Multi-Gigabit Interconnect Chip
VITESSE
G52352-0, Rev 3.2
05/05/01
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Loopback Operation
Loop back control pins, LBENn(1:0), are provided in each channel to internally loopback data paths for on-
chip diagnosis. Both serial and parallel loopback functions are provided.
Table 9: Loopback Mode Selection
When LBENn(1:0)=10, Serial Loopback mode is selected, the transmitter
’
s serial transmit data is internally
connected to the receiver
’
s CRU input. The serial loopback paths are labeled LBTXn in the VSC7216-01 block
diagram on the first page. This allows parallel data on Tn(7:0) to be encoded, serialized, looped back,
deserialized and decoded. This mode is intended for the system to verify functionality of the local VSC7216-01
prior to attempting to establish an external link. The PTXn and RTXn outputs are unaffected by the state of
LBENn(1:0).
When LBENn(1:0)=01, Parallel Loopback mode is selected. The Rn(7:0) outputs are looped back to the
Tn(7:0) inputs (Figure 11). WSENn does not have a loopback source and is internally connected to a logic
LOW. KCHAR does not have a loopback source and is internally connected to a logic HIGH. The C/Dn input is
obtained by decoding the link status outputs such that either a data character, special character, or IDLE (K28.5)
is transmitted. When the link is in the LOS or RESYNC states, C/Dn is asserted and the data path is set to 0xBC
so that an IDLE will be transmitted. For other link status conditions C/Dn follows the KCHn status bit. This
guarantees that IDLE and special characters will be correctly looped back along with normal data, and also has
the effect of looping back the data received as a normal data character when a disparity error, out-of-band
character, or underflow/overflow link status condition occurs.
Figure 11: Parallel Loopback Mode Operation
LBENn(1:0)
Loopback Mode
0 0
Normal Operation
0 1
Internal Parallel Loopback
1 0
Internal Serial Loopback
1 1
Reserved
10
Encode
8B/10B
D Q
Tn(7:0)
C/Dn
WSENn
a
REFCLK
8
8
PTXn-
RTXn+
RTXENn
PTXENn
PRXn-
RRXn+
RXP/Rn
LBENn(1:0)
Recovery
Clk/Data
Decode
8B/10B
10
Buffer
Elastic
3
8
IDLEn
KCHn
ERRn
Rn(7:0)
8
TRANSMITTER
RECEIVER
LBTXn
RSDETn
a
REFCLK
LBTXn
1
0
KCHAR
PARLOOP
1
0
1
0
(dec)
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