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參數(shù)資料
| 型號(hào)： | VS28F016SV |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Mbit(1MBitx16) FLASHFILE MEMORY(16M位FLASHFILE存儲(chǔ)器) |
| 中文描述： | 16兆位（1MBitx16）FLASHFILE記憶（1,600位FLASHFILE存儲(chǔ)器） |
| 文件頁數(shù)： | 7/50頁 |
| 文件大?。?/td> | 612K |
| 代理商： | VS28F016SV |
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VS28F016SV, MS28F016SV FlashFile
TM
Memory
2.1 Lead Descriptions
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not
used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE
Y
is high).
A
1
- A
15
INPUT
WORD-SELECT ADDRESSES:
Select a word within one 64-Kbyte
block. A
6-15
selects 1 of 1024 rows, and A
1-5
selects 16 of 512
columns. These addresses are latched during Data Writes.
A
16
- A
20
INPUT
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQ
0
- DQ
7
INPUT/OUTPUT
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the
appropriate read mode. Floated when the chip is de-selected or the
outputs are disabled.
DQ
8
- DQ
15
INPUT/OUTPUT
HIGH-BYTE DATA BUS:
Inputs data during x16 Data-Write
operations. Outputs array, buffer or identifier data in the appropriate
read mode; not used for Status Register reads. Floated when the
chip is de-selected or the outputs are disabled.
CE
0
Y
, CE
1
Y
INPUT
CHIP ENABLE INPUTS:
Activate the device’s control logic, input
buffers, decoders and sense amplifiers. With either CE
0
Y
or CE
1
Y
high, the device is de-selected and power consumption reduces to
standby levels upon completion of any current Data-Write or Erase
operations. Both CE
0
Y
, CE
1
Y
must be low to select the device.
All timing specifications are the same for both signals. Device
Selection occurs with the latter falling edge of CE
0
Y
or CE
1
Y
. The
first rising edge of CE
0
Y
or CE
1
Y
disables the device.
RESET/POWER-DOWN:
RP
Y
low places the device in a Deep
Power-Down state. All circuits that consume static power, even those
circuits enabled in standby mode, are turned off. When returning from
Deep Power-Down, a recovery time of t
PHQV
at 5.0V V
CC
is required
to allow these circuits to power-up.
When RP
Y
goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to
ready (with all status flags cleared).
Exit from Deep Power-Down places the device in read array mode.
RP
Y
INPUT
OE
Y
INPUT
OUTPUT ENABLE:
Gates device data through the output buffers
when low. The outputs float to tri-state off when OE
Y
is high.
NOTE:
CE
x
Y
overrides OE
Y
, and OE
Y
overrides WE
Y
.
WE
Y
INPUT
WRITE ENABLE:
Controls access to the CUI, Page Buffers, Data
Queue Registers and Address Queue Latches. WE
Y
is active low,
and latches both address and data (command or array) on its rising
edge. Page Buffer addresses are latched on the falling edge of WE
Y
.
7
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