參數資料
型號: VS1003
廠商: Electronic Theatre Controls, Inc.
元件分類: Codec
英文描述: MP3 / WMA AUDIO CODEC
中文描述: MP3播放/ WMA音頻編解碼器
文件頁數: 44/57頁
文件大?。?/td> 456K
代理商: VS1003
VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
10. VS1003 REGISTERS
10.8
Interrupt Registers
Interrupt registers, prefix INT
Abbrev[bits]
ENABLE[7:0]
GLOB DIS[-]
GLOB ENA[-]
COUNTER[4:0]
Reg
Type
rw
w
w
rw
Reset
0
0
0
0
Description
Interrupt enable.
Write to add to interrupt counter.
Write to subtract from interript counter.
Interrupt counter.
0xC01A
0xC01B
0xC01C
0xC01D
INT ENABLE controls the interrupts. The control bits are as follows:
INT ENABLE bits
Description
Enable Timer 1 interrupt.
Enable Timer 0 interrupt.
Enable UART RX interrupt.
Enable UART TX interrupt.
Enable AD modulator interrupt.
Enable Data interrupt.
Enable SCI interrupt.
Enable DAC interrupt.
Name
INT EN TIM1
INT EN TIM0
INT EN RX
INT EN TX
INT EN MODU
INT EN SDI
INT EN SCI
INT EN DAC
Bits
7
6
5
4
3
2
1
0
Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.
Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively
disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.
Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER
already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are re-
stored. An interrupt routine should always write to this register as the last thing it does, because in-
terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the
responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register
is not 0, interrupts are disabled.
Version 0.92,
2005-06-07
44
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