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參數(shù)資料
| 型號： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 20/57頁 |
| 文件大小： | 456K |
| 代理商： | VS1003 |
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VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
7. SPI BUSES
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
After the last bit has been sent, DREQ is driven low for the duration of the register update, marked “exe-
cution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.6
for details). If the maximum time is longer than what it takes from the microcontroller to feed the next
SCI command or SDI byte, it is not allowed to finish a new SCI/SDI operation before DREQ has risen
up again.
7.6
SPI Timing Diagram
XCS
SCK
SI
SO
0
1
15
14
16
tXCSS
tXCSH
tWL
tWH
tH
tSU
tV
tZ
tDIS
tXCS
30
31
Figure 8: SPI Timing Diagram.
Symbol
tXCSS
tSU
tH
tZ
tWL
tWH
tV
tXCSH
tXCS
tDIS
Min
Max
Unit
ns
ns
CLKI cycles
ns
CLKI cycles
CLKI cycles
CLKI cycles
ns
CLKI cycles
ns
5
-26
2
0
2
2
2 (+ 25ns
1
)
-26
2
10
1
25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1003’s internal clock speed CLKI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in
1
.
0
×
mode, thus CLKI
=
XTALI.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 0.92,
2005-06-07
20
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相關(guān)代理商/技術(shù)參數(shù) |
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| VS100AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CAMERA MONOCHROME |
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