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參數(shù)資料
| 型號(hào)： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 37/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | VS1003 |
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VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
9. OPERATION
9
Operation
9.1
Clocking
VS1003 operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock
canbegeneratedbyexternalcircuitry(connectedtopinXTALI)orbytheinternalclockchrystalinterface
(pins XTALI and XTALO).
9.2
Hardware Reset
When the XRESET -signal is driven low, VS1003 is reset and all the control registers and internal states
are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1003 are in minimum
power consumption stage, and where clocks are stopped. Also XTALO is grounded.
After a hardware reset (or at power-up) DREQ will stay down for at least 16600 clock cycles, which
means an approximate 1.35 ms delay if VS1003 is run at 12.288 MHz. After this the user should set
such basic software registers as SCI MODE, SCI BASS, SCI CLOCKF, and SCI VOL before starting
decoding. See section 8.6 for details.
Internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF register
are
1
.
0
...
4
.
5
the input clock. Reset value for Internal Clock Multiplier is
1
.
0
. If typical values
are wanted, the Internal Clock Multiplier needs to be set to
3
.
0
after reset. Wait until DREQ rises, then
write value 0x9800 to SCI CLOCKF (register 3). See section 8.6.4 for details.
9.3
Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.6.1). Then wait for at least 2
μ
s, then look at DREQ. DREQ will stay down for at least 16600
clock cycles, which means an approximate 1.35 ms delay if VS1003 is run at 12.288 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1003 doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros (honoring DREQ) to the SDI bus after the file
and before the reset. This is especially important for MIDI files, although you can also use SCI HDAT1
polling.
If you want to interrupt the playing of a WAV, WMA, or MIDI file in the middle, set SM OUTOFWAV in
the mode register, and wait until SCI HDAT1 is cleared (with a two-second timeout) before continuing
with a software reset. MP3 does not currently implement the SM OUTOFWAV because it is a stream
format, thus the timeout requirement.
Version 0.92,
2005-06-07
37
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相關(guān)代理商/技術(shù)參數(shù) |
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| VS1003-BB | 制造商:Distributed By MCM 功能描述:VS1003 MP3/WMA BREAKOUT BOARD |
| VS1003B-L | 制造商:CONSONANCE 制造商全稱:CONSONANCE 功能描述:芬蘭VLSI廠家生產(chǎn)的音頻編解碼芯片 |
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| VS100AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CAMERA MONOCHROME |
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