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參數(shù)資料
| 型號： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
7
4.2
Signal Description
This chapter provides a detailed description of Vortex86SX signals. A signal with the symbol ”_n” at the end of itself indicates
that this pin is low active. Otherwise, it is high active.
The following notations are used to describe the signal types:
I
Input pin
O
Output pin
OD
Output pin with open-drain
I/O
Bi-directional Input/Output pin
z
System (7 PINs)
PIN No.
Symbol
Type
Description
AA26
PWRGOOD
I
Power-Good Input.
This signal comes from Power Good of the power supply
to indicate that the power is available. The Vortex86SX uses this signal to
generate reset sequence for the system.
25MHz Clock output.
Crystal-out
. Frequency output from the inverting amplifier (oscillator).
Crystal-in.
14.318MHz frequency input, within 100 ppm tolerance, to the
amplifier (oscillator).
MTBF Flag output.
24MHz Clock output
Speaker Output.
This pin is used to control the Speaker Output and should
be connected to the Speaker
AB26
Y26
25MOUT
XOUT_14.318
O
O
Y25
XIN_14.318
I
AA25
AB25
MTBF
CLK24MOUT
O
Y23
SPEAKER
O
z
SDRAM /DDRII Interface (44 PINs)
PIN No.
Symbol
Type
Description
B9
SDRAMCLK
O
Clock output.
This pin provides the fundamental timing for the SDRAM /DDR
controller.
Clock output.
This pin provides the fundamental timing for the SDRAM /DDR
controller.
Row Address Strobe.
When asserted, this signal latches row address on
positive edge of the SDRAM/DDR clock. This signal also allows row access
and pre-charge.
Column Address Strobe.
When asserted, this signal latches column address
on the positive edge of the SDRAM/DDR clock. This signal also allows
column access and pre-charge.
Memory Write Enable.
This pin is used as a write enable for the memory
data bus.
Chip Select CS[1:0].
These two pins activate the SDRAM devices. First Bank
of SDRAM accepts any command when the CS0_n pin is active low. Second
Bank of SDRAM accepts any command when the CS1_n pin is active low.
For DDRII, only CS0_n activates the DDR device.
Data Mask DQM[1:0].
These pins act as synchronized output enables during
read cycles and byte masks during write cycles.
Data Strobe DQS[1:0 for DDR only.
Output with write data, input with the
read data for source synchronous operation.
A9
SDRAMCLKN
O
D13
RAS_
O
E12
CAS_
O
C13
WE_
O
B13, E13
CS_[1:0]
O
B14, D17
DQM[1:0]
O
E16, D14
DQS[1:0]
I/O
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