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參數(shù)資料
| 型號： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
13
AE23
CTS1/GPIO_P4[7]
I/O
Clear to Send.
This active low input for the primary and secondary serial
ports. A handshake signal notifies the UART that the modem is ready to
receive data. The CPU can monitor the status of the CTS_n signal by reading
bit 4 of Modem Status Register (MSR). A CTS_n signal states the change
from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3
of the Interrupt Enable Register is set, the interrupt is generated when CTS_n
changes the state. The CTS_n signal has no effect on the transmitter.
Note:
Bit 4 of the MSR is the complement of CTS_n.
General-Purpose Input/Output GPIO port4 [7].
Data Set Ready.
This active low input is for the UART ports. A handshake
signal notifies the UART that the modem is ready to establish the
communication link. The CPU can monitor the status of the DSR_n signal by
reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the
change from low to high after the last MSR read sets bit1 of the MSR to a “1”.
If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when
DSR_n changes state.
Note:
Bit 5 of the MSR is the complement of DSR_n.
General-Purpose Input/Output GPIO port4 [6].
Data Carrier Detect.
This active low input is for the UART ports. A handshake
signal notifies the UART that the carrier signal is detected by the modem. The
CPU can monitor the status of the DCD_n signal by reading bit 7 of the
Modem Status Register (MSR). A DCD_n signal states the change from low to
high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the
Interrupt Enable Register is set, the interrupt is generated when DCDJ
changes state.
Note:
Bit 7 of the MSR is the complement of DCD_n.
General-Purpose Input/Output GPIO port4 [0].
Ring Indicator.
This active low input is for the UART ports. A handshake
signal notifies the UART that the telephone ring signal is detected by the
modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of
the Modem Status Register (MSR). An RI_n signal states the change from low
to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the
Interrupt Enable Register is set, the interrupt is generated when RI_n changes
state.
Note:
Bit 6 of the MSR is the complement of RI_n.
General-Purpose Input/Output GPIO port4 [3].
Data Terminal Ready.
This is an active low output for the UART port. A
handshake output signal signifies the modem that the UART is ready to
establish data communication link. This signal can be programmed by writing
to bit 0 of Modem Control Register (MCR). The hardware reset will clear the
DTR_n signal to be inactive during the loop-mode operation.
General-Purpose Input/Output GPIO port4 [5].
COM1 TX Status.
This pin will be high when COM1 is trnamitting.
AF23
DSR1/GPIO_P4[6]
I/O
AF24
DCD1/GPIO_P4[0]
I/O
AD22
RI1/GPIO_P4[3]
I/O
AD23
DTR1/GPIO_P4[5]
I/O
AD21
TXD_EN1
I/O
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| VOS615A-2X001T | 功能描述:晶體管輸出光電耦合器 CTR 63-125% 10MA RoHS:否 制造商:Vishay Semiconductors 輸入類型:DC 最大集電極/發(fā)射極電壓:70 V 最大集電極/發(fā)射極飽和電壓:0.4 V 絕緣電壓:5300 Vrms 電流傳遞比:100 % to 200 % 最大正向二極管電壓:1.65 V 最大輸入二極管電流:60 mA 最大集電極電流:100 mA 最大功率耗散:100 mW 最大工作溫度:+ 110 C 最小工作溫度:- 55 C 封裝 / 箱體:DIP-4 封裝:Bulk |
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