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參數(shù)資料
| 型號(hào)： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁(yè)數(shù)： | 10/30頁(yè) |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
10
C20, B20, A21
A22, A23, A24,
A25, B26, D20,
E20, C21, B21,
C22, B22, C23,
B23, E24, E25,
E26, H22, G23,
F26, F25, H21,
G25, J22, G26,
H25, H26, J25,
J26, H24
AD[31:0]
I/O
PCI Address and Data.
The standard PCI address and data lines. The
address is driven with PCI Frame assertion and data is driven or received in
the following clocks.
B25, B24, G22,
F24
CBE_[3:0]
I/O
Bus Command and Byte Enables.
During the address phase, C/BE_n[3:0]
define the Bus Command. During the data phase, C/BE[3:0]_n define the Byte
Enables.
PCI Frame
.
This pin
is driven by a PCI master to indicate the beginning and
duration of a PCI transaction.
PCI Initiator Ready.
This pin is asserted low by the master to indicate that it
is able to transfer the current data transfer. A data was transferred if both
IRDY_n and TRDY_n are asserted low during the rising edge of the PCI
clock.
PCI Target Ready
.
This pin is asserted low by the target to indicate that it is
able to receive the current data transfer. A data was transferred if both
IRDY_n and TRDY_n are asserted low during the rising edge of the PCI
clock.
Device Select.
This pin is driven by the devices which have decoded the
addresses belonging to them.
PCI Stop.
This pin is asserted low by the target to indicate that it is unable to
receive the current data transfer.
PCI Parity
.
This pin is driven to even parity by PCI master over the AD[31:0]
and C/BE_n[3:0] bus during address and write data phases. It should be
pulled high through a weak external pull-up resistor. The target drives parity
during data read.
PCI INTA_.
PCI interrupt input A. It connects to PCI INTA_n when normal
modes of PCI Interrupts are supported.
PCI INTB_.
PCI interrupt input B. It connects to PCI INTB_n when normal
modes of PCI Interrupts are supported.
PCI INTC_.
PCI interrupt input C. It connects to PCI INTC_n when normal
modes of PCI Interrupts are supported.
PCI INTD_.
PCI interrupt input D. It connects to PCI INTD_n when normal
modes of PCI Interrupts are supported.
C24
FRAME_
I/O
C25
IRDY_
I/O
C26
TRDY_
I/O
D24
DEVSEL_
I/O
D25
STOP_
I/O
G24
PAR
I/O
H23
INTA_
I
F19
INTB_
I
F20
INTC_
I
E19
INTD_
I
z
EXTERNAL SPI/PORT[3-0] Interface (4 PINs)
PIN No.
Symbol
Type
Description
W21
E_SPI_CS_/GPIO_P3[0]
I/O
External SPI Chip Select
General-Purpose Input/Output P3[0]
External SPI Clock
General-Purpose Input/Output P3[1]
External SPI Data Ouput
General-Purpose Input/Output P3[2]
External SPI Data Input
General-Purpose Input/Output P3[3]
W22
E_SPI_CLK/GPIO_P3[1]
I/O
Y21
E_SPI_DO/GPIO_P3[2]
I/O
Y22
E_SPI_DI/GPIO_P3[3]
I/O
z
ISA Bus Interface ( 87 PINs)
PIN No.
Symbol
Type
Description
AA13
IOCHCK_
I
I/O Channel Check
. Provides the system board with parity (error) information
about memory or devices on the I/O channel.
ISA high and low byte slot data bus
. These are the system data lines.
These signals read data and vectors into CPU during memory or I/O read
cycles or interrupt acknowledge cycles and outputs data from CPU during
AE16, AF16, AD10,
AF15, AF14, AE11,
AE10, AD12,Y6,
AD14, Y4, AA14,
SD[15:0]
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VOYAGER | Voyager Emulation Platform (ATV1) Summary [Updated 3/02. 2 Pages] This document gives the key features. a brief description and an illustration. The Complete is available under Non-Disclosure Agreement. |
| VP-1000A | Digital Voice Processor |
| VP-1000AF | Digital Voice Processor |
| VP-1608F | Digital Voice Processor |
| VP0104 | P-Channel Enhancement-Mode Vertical DMOS FET(擊穿電壓-40V,8Ω，P溝道增強(qiáng)型垂直DMOS結(jié)構(gòu)場(chǎng)效應(yīng)管) |
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