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參數(shù)資料
| 型號： | VORTEX86SX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-BIT x86 Embedded SoC |
| 中文描述： | 32位x86嵌入式系統(tǒng)芯片 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 2964K |
| 代理商： | VORTEX86SX |
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Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
16
L4
ACK_/SDD11
I/O
ACK_.
An active low input on this pin indicates that the printer has received
data and is ready to accept more data. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
SLIN_.
Output line for detection of printer selection. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
INIT_.
Output line for the printer initialization. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
ERR_.
An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of the parallel port for
the definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
AFD_.
An active low output from this pin causes the printer to auto feed a line
after a line is printed. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
IDE Secondary Channel Data Bus.
Request to Send.
Active low Request to Send output for UART port.
A handshake output signal notifies the modem that the UART is ready to
transmit data. This signal can be programmed by writing to bit 1 of Modem
Control Register (MCR). The hardware reset will clear the RTS_n signal to be
inactive mode (high). It is forced to be inactive during the loop-mode
operation.
IDE Secondary Channel Reset.
Data Carrier Detect.
This active low input is for the UART ports. A handshake
signal notifies the UART that the carrier signal is detected by the modem. The
CPU can monitor the status of the DCD_n signal by reading bit 7 of the
Modem Status Register (MSR). A DCD_n signal states the change from low to
high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the
Interrupt Enable Register is set, the interrupt is generated when DCDJ
changes state.
Note:
Bit 7 of the MSR is the complement of DCD_n.
IDE Secondary Channel DMA Request.
Clear to Send.
This active low input for the primary and secondary serial
ports. A handshake signal notifies the UART that the modem is ready to
receive data. The CPU can monitor the status of the CTS_n signal by reading
bit 4 of Modem Status Register (MSR). A CTS_n signal states the change
from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3
of the Interrupt Enable Register is set, the interrupt is generated when CTS_n
changes the state. The CTS_n signal has no effect on the transmitter.
Note:
Bit 4 of the MSR is the complement of CTS_n.
IDE Secondary Channel IO Write Strobe.
Clear to Send.
This active low input for the primary and secondary serial
ports. A handshake signal notifies the UART that the modem is ready to
receive data. The CPU can monitor the status of the CTS_n signal by reading
bit 4 of Modem Status Register (MSR). A CTS_n signal states the change
from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3
of the Interrupt Enable Register is set, the interrupt is generated when CTS_n
changes the state. The CTS_n signal has no effect on the transmitter.
Note:
Bit 4 of the MSR is the complement of CTS_n.
IDE Secondary Channel IO Read Strobe.
M3
SLIN_/SDD12
SLIN_: OD
SDD12: I/O
J1
INIT_/SDD13
INIT_: OD
SDD13: I/O
N4
ERR_/SDD14
I/O
L3
AFD_/SDD15
AFD_: OD
SDD15: I/O
H3
RTS3_/SRST_
O
J2
DCD3_/SDRQ
I
P6
CTS4_/SIOW_
I/O
H2
CTS3_/SIOR_
I/O
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