參數(shù)資料
型號: V917564B28QAFW-D3
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200
封裝: ROHS COMPLIANT, SODIMM-200
文件頁數(shù): 6/17頁
文件大小: 114K
代理商: V917564B28QAFW-D3
V916764B24QA Rev 1.3 March 2007
14
V916764B24QA
ProMOS TECHNOLOGIES
DQS falling edge from CLK rising Hold Time
tDSH
0.2
-
0.2
-
0.2
-
CLK
DQ & DM Input Pulse Width
tDIPW
0.35
-
0.35
-
0.35
-
CLK
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
CLK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
0.25
-
CLK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Internal read to precharge command delay
tRTP
7.5
-
7.5
-
7.5
-
ns
Internal write to read command delay
tWTR
10
-
7.5
-
7.5
-
ns
Data out high impedance time from CLK/CLK
tHZ
tAC(min)
tAC(max)
tAC(min)
tAC(max)
tAC(min)
tAC(max)
ns
Data out low impedance time from CLK/CLK
tLZ
tAC(min)
tAC(max)
tAC(min)
tAC(max)
tAC(min)
tAC(max)
ns
Mode Register Set Delay
tMRD
2-
2
-
2
-
CLK
Exit Self Refresh to Non-Read Command
tXSNR
tRFC+10
-
tRFC+10
-
tRFC+10
-
ns
Exit Self Refresh to Read Command
tXSRD
200
-
200
-
200
-
CLK
Exit Precharge Power Down to any non-Read
Command
tXP
2
-
2
-
2
-
CLK
Exit Active Power Down to Read Command
tXARD
2-
2
-
2
-
CLK
Exit Active Power Down to Read Command
(Slow exit, Lower Power)
tXARDS
6-AL
-
6-AL
-
6-AL
-
CLK
ODT drive mode output delay
tOIT
012
0
12
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
CKE minimum high and low pulse width
tCKE
3-
3
-
3
-
CLK
Average Periodic Refresh Interval
0C < T < 85C
tREFI
-
7.8
-
7.8
-
7.8
us
Parameter
Symbol
(DDR2-400)
-5
(DDR2-533)
-37
(DDR2-667)
-3
Unit
Min
Max
Min
Max
Min
Max
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