參數(shù)資料
型號(hào)： V917564B28QAFW-D3
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200
封裝： ROHS COMPLIANT, SODIMM-200
文件頁(yè)數(shù)： 14/17頁(yè)
文件大?。?/td> 114K
代理商： V917564B28QAFW-D3
V916764B24QA Rev 1.3 March 2007
6
V916764B24QA
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D3 (PC2-3200 @ CL3)
F5 (PC2-5300 @ CL5)
E4 (PC2-4200 @ CL4)
Byte #
Function described
Function Supported
Hex value
D3
E4
F5
D3
E4
F5
0
Defines # of Bytes written into serial memory at module manufac-
turer
128bytes
80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR2
08h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
10
0Ah
5
Module attributes-Number of DIMM Ranks, Package and Height
1.18in., Dual rank
61h
6
Data width of this assembly
64 bits
40h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 1.8V
05h
9
DDR SDRAM cycle time at CL=X
5ns
3.75ns
3.0ns
50h
3Dh
30h
10
DDR SDRAM Access time from clock at CL=X
±0.6ns
±0.50ns
±0.45ns
60h
50h
45h
11
DIMM configuration type(Non-parity, Parity, ECC)
Unbuffered
00h
12
Refresh rate & type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x16
10h
14
Error checking DDR SDRAM data width
N/A
00h
15
Reserved
-
00h
16
DDR SDRAM device attributes : Burst lengths supported
4,8
0Ch
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency supported
3,4,5
38h
19
Reserved
-
00h
20
DDR2 DIMM Type
SODIMM
04h
21
DDR2 SDRAM module attributes
-
00h
22
DDR2 SDRAM device attributes : General
Support weak driver (D3/E4)
Support ODT=50ohm/PASR/
Weak driver (F5)
01h
07h
23
DDR SDRAM cycle time at CL=X-1
5ns
3.75ns
50h
3Dh
24
DDR SDRAM Access time from CL=X-1
±0.6ns
±0.50ns
±0.45ns
60h
50h
45h
25
DDR SDRAM cycle time at CL=X-2
5.0ns
50h
26
DDR SDRAM Access time from CL=X-2
±0.60ns
60h
27
Minimum row precharge time (=tRP)
15ns
3Ch
28
Minimum row activate to row active delay (=tRRD)
10ns
28h
29
Minimum RAS to CAS delay (=tRCD)
15ns
3Ch
相關(guān)PDF資料
PDF描述
V91F564U24QBFW-F5 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
VA2ARG-FREQ VCXO, CLOCK, 1 MHz - 100 MHz, HCMOS OUTPUT
VA2TSL-77.760 VCXO, CLOCK, 77.76 MHz, HCMOS OUTPUT
VA2TUF-38.880 VCXO, CLOCK, 38.88 MHz, HCMOS OUTPUT
VA2TUH-27.000 VCXO, CLOCK, 27 MHz, HCMOS OUTPUT
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