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參數(shù)資料
| 型號(hào)： | V917564B28QAFW-D3 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 114K |
| 代理商： | V917564B28QAFW-D3 |
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V916764B24QA Rev 1.3 March 2007
5
V916764B24QA
ProMOS TECHNOLOGIES
Pin Description
Symbol
Type
Function
Input
CKE0-CKE1
Input
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivat-
ing the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode
Input
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disbled, new command are ignored but previous opera-
tions continue. This signal provides for external rank selection on systems with multiple ranks
Input
ODT0-ODT1
Input
VREF
Supply
Reference voltage for SSTL 18 inputs.
VDDQ
Supply
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all cur-
rent DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA1
Input
Selects which SDRAM BANK of four is activated.
A0-A13
Input
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If
AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction
with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
DQ0-DQ63
CB0-CB7
In/Out
Data and Check Bit Input/Output pins.
DM0-DM8
Input
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident
with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
VDD,VSS
Supply
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
VDD/VDDQ planes on these modules.
DQS0-DQS8
In/Out
Data strobe for input and output data. its edge-aligned with read data, center aligned with write data.
SA0-SA2
Input
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EER-
POM address range.
SDA
In/Out
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDD to act as a pullup on the system board.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pullup onthe system board.
VDD SPD
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
CK0-CK2
CK0#-CK2#
RAS#, CAS#, WE#
S0#- S1#
CK and CK# are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing
of positive edge of CK and negative edge of CK#. Output (read) data is reference to the crossing of
CK and CK# (Both directions of crossing)
RAS#, CAS#, WE# (ALONG WITH CS#) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ# and DM pins, assuming the function is
enabled in the Extended Mode Register Set (EMRS).
DQS0#-DQS8#
DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.
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