參數(shù)資料
型號(hào)： V917564B28QAFW-D3
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200
封裝： ROHS COMPLIANT, SODIMM-200
文件頁數(shù)： 15/17頁
文件大小： 114K
代理商： V917564B28QAFW-D3
V916764B24QA Rev 1.3 March 2007
7
V916764B24QA
ProMOS TECHNOLOGIES
30
Minimum active to precharge time (=tRAS)
40ns
39ns
28h
27h
31
Module Rank density
256MB
40h
32
Command and address signal input setup time
0.35ns
0.25ns
0.20ns
35h
25h
20h
33
Command and address signal input hold time
0.47ns
0.37ns
0.32ns
47h
37h
32h
34
Data signal input setup time
0.15ns
0.10ns
0.05ns
15h
10h
05h
35
Data signal input hold time
0.27ns
0.22ns
0.17ns
27h
22h
17h
36
Write Recovery Time (=tWR)
15ns
3Ch
37
Write to Read CMD delay (=tWTR)
10ns
7.5ns
28h
1Eh
38
Read to Precharge CMD delay (=tRTP)
7.5ns
1Eh
39
Mem Analysis Probe
00
40
Extension for bytes 41 and 42
00
41
SDRAM device minimum active to active/auto-refresh time (=tRC)
55ns
54ns
37h
36h
42
SDRAM device minimum active to autorefresh to active/auto-re-
fresh time (=tRFC)
105ns
69h
43
SDRAM device maximum device cycle time (=tCK MAX)
8ns
80h
44
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.35ns
0.3ns
0.25ns
23h
1Eh
19h
45
SDRAM device maximum read datahold skew factor (=tQHS)
0.45ns
0.40ns
0.35ns
2Dh
28h
23h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release 1.0
10h
63
Checksum for Bytes 0 ~ 62
-
FEh
7Ah
31h
64
Manufacturer JEDEC ID code
ProMOS
40h
65 -71
....... Manufacturer JEDEC ID code
00h
72
Manufacturing location
02=Taiwan 05=China 0A=S-CH
04=Malaysia
73-90
Module part number (ASCII)
V916764B24QA
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Year) in BCD. Example: Year 2006 = 06h
-
94
Manufacturing date (Week) in BCD. Example: Week 28 = 28h
-
95~98
Assembly serial #
-
99~127
Manufacturer specific data (may be used in future)
Undefined
00h
128~255 Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
D3
E4
F5
D3
E4
F5
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