- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359326 > V58C265404S (Mosel Vitelic, Corp.) HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 PDF資料下載
參數(shù)資料
| 型號： | V58C265404S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| 中文描述： | 高性能2.5伏16米x 4 DDR SDRAM的4銀行X的4Mb × 4 |
| 文件頁數(shù)： | 1/44頁 |
| 文件大?。?/td> | 391K |
| 代理商： | V58C265404S |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
MOSEL VITELIC
1
V58C265404S
HIGH PERFORMANCE
2.5 VOLT 16M X 4 DDR SDRAM
4 BANKS X 4Mbit X 4
V58C265404S Rev. 1.4 January 2000
PRELIMINARY
6
7
8
System Frequency (f
CK
)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
8 ns
Clock Cycle Time (t
CK2.5
)
6.5 ns
7.5 ns
9 ns
Clock Cycle Time (t
CK2
)
7ns
8ns
10ns
Features
I
4 banks x 4Mbit x 4 organization
I
High speed data transfer rates with system
frequency up to 166 MHz
I
Data Mask for Write Control (DM)
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 2.5, 3
I
Programmable Wrap Sequence: Sequential
or Interleave
I
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
I
Automatic and Controlled Precharge Command
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 66-pin 400 mil TSOP-II
I
SSTL-2 Compatible I/Os
I
Double Data Rate (DDR)
I
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
I
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
I
Differential clock inputs CLK and CLK
I
Power supply 2.5V
±
0.2V
Description
The V58C265404S is a four bank DDR DRAM or-
ganized as 4 banks x 4Mbit x 4. The V58C265404S
achieves high speed data transfer rates by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOPII
–6
-7
-8
Std.
L
0
°
C to 70
°
C
Blank
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C265804S | HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
| V58C3643204SAT | HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| V58C365164S | 64 Mbit DDR SDRAM 4M X 16, 3.3VOLT |
| V602AS32 | High Energy Metal-Oxide Arrester Blocks |
| V604ME03 | VOLTAGE CONTROLLED OSCILLATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C265804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
| V58C3643204SAT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| V58C365164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:64 Mbit DDR SDRAM 4M X 16, 3.3VOLT |
| V590ME01 | 制造商:ZCOMM 制造商全稱:ZCOMM 功能描述:LOW COST - HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR |
| V590ME01-LF | 制造商:ZCOMM 制造商全稱:ZCOMM 功能描述:Voltage-Controlled Oscillator Surface Mount Module |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。