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參數(shù)資料
| 型號： | V58C265804S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
| 中文描述： | 高性能2.5伏8米× 8 DDR SDRAM的4銀行X 2Mbit的× 8 |
| 文件頁數(shù)： | 1/44頁 |
| 文件大小： | 457K |
| 代理商： | V58C265804S |
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MOSEL VITELIC
1
V58C265804S
HIGH PERFORMANCE
2.5 VOLT 8M X 8 DDR SDRAM
4 BANKS X 2Mbit X 8
V58C265804S Rev. 1.3 January 2000
PRELIMINARY
6
7
8
System Frequency (f
CK
)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
8 ns
Clock Cycle Time (t
CK2.5
)
6.5 ns
7.5 ns
9 ns
Clock Cycle Time (t
CK2
)
7ns
8ns
10ns
Features
I
4 banks x 2Mbit x 8 organization
I
High speed data transfer rates with system
frequency up to 166 MHz
I
Data Mask for Write Control (DM)
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 2.5, 3
I
Programmable Wrap Sequence: Sequential
or Interleave
I
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
I
Automatic and Controlled Precharge Command
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 66-pin 400 mil TSOP-II
I
SSTL-2 Compatible I/Os
I
Double Data Rate (DDR)
I
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
I
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
I
Differential clock inputs CLK and CLK
I
Power Supply 2.5V
±
0.2V
Description
The V58C265804S is a four bank DDR DRAM or-
ganized as 4 banks x 2Mbit x 8. The V58C265804S
achieves high speed data transfer rates by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
–6
-7
-8
Std.
L
0
°
C to 70
°
C
Blank
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