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參數(shù)資料
| 型號(hào)： | V58C3643204SAT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| 中文描述： | 高性能3.3伏200萬(wàn)× 32 DDR SDRAM的4 × 512k × 32的 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 278K |
| 代理商： | V58C3643204SAT |
MOSEL VITELIC
1
V58C3643204SAT
HIGH PERFORMANCE
3.3 VOLT 2M X 32 DDR SDRAM
4 X 512K X 32
V58C3643204SAT Rev. 1.4 August 2001
PRELIMINARY
45
50
55
60
System Frequency (f
CK
)
225MHz
200 MHz
183 MHz
166 MHz
Clock Cycle Time (t
CK3
)
5 ns
5.5 ns
6 ns
Clock Cycle Time (t
CK4
)
4.5 ns
Features
I
4 banks x 512K x 32 organization
I
High speed data transfer rates with system
frequency up to 225 MHz
I
Data Mask for Write Control (DM)
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 3, 4
I
Programmable Wrap Sequence: Sequential
or Interleave
I
Programmable Burst Length:
2, 4, 8 full page for Sequential Type
2, 4, 8 full page for Interleave Type
I
Automatic and Controlled Precharge Command
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 2048 cycles/16ms
I
Available in 100-pin TQFP
I
SSTL-2 Compatible I/Os
I
Double Data Rate (DDR)
I
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
I
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
I
Differential clock inputs CLK and CLK
I
Power Supply 3.3V ± 0.3V
Description
The V58C3643204SAT is a four bank DDR
DRAM organized as 4 banks x 512K x 32. The
V58C3643204SAT
achieves
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
high
speed
data
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
100-pin TQFP
-45
-50
-55
-60
Std.
L
0°C to 70°C
Blank
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