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參數(shù)資料
| 型號： | V58C365164S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 64 Mbit DDR SDRAM 4M X 16, 3.3VOLT |
| 中文描述： | 64兆位DDR SDRAM的4米× 16，3.3VOLT |
| 文件頁數(shù)： | 1/44頁 |
| 文件大?。?/td> | 516K |
| 代理商： | V58C365164S |
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MOSEL VITELIC
1
V58C365164S
64 Mbit DDR SDRAM
4M X 16, 3.3VOLT
V58C365164S Rev. 1.7 March 2002
PRELIMINARY
36
4
5
System Frequency (f
CK
)
275 MHz
250 MHz
200 MHz
Clock Cycle Time (t
CK3
)
3.6 ns
4 ns
5 ns
Clock Cycle Time (t
CK2.5
)
4.3ns
4.8 ns
6 ns
Clock Cycle Time (t
CK2
)
5.4ns
6 ns
7.5 ns
Features
■
4 banks x 1Mbit x 16 organization
■
High speed data transfer rates with system
frequency up to 275 MHz
■
Data Mask for Write Control (DM)
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Suspend Mode and Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 4096 cycles/64 ms
■
Available in 66-pin 400 mil TSOP-II
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
■
Differential clock inputs CLK and CLK
■
Power supply 3.3V ± 0.3V
■
VDDQ (I/O) power supply 2.5 + 0.2V
Description
The V58C365164S is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C365164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
-36
-4
-5
Std.
L
0°C to 70°C
Blank
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