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參數(shù)資料
| 型號(hào)： | V54C365804VCT8L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 7/54頁(yè) |
| 文件大?。?/td> | 453K |
| 代理商： | V54C365804VCT8L |
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15
V54C365804VC Rev. 0.6 September 1999
MOSEL VITELIC
V54C365804VC
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Full Page Burst Write Operation
8.2 Termination of a Full Page Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 2
12. 2 Clock Suspension During Burst Read CAS Latency = 3
12. 3 Clock Suspension During Burst Write CAS Latency = 2
12. 4 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Self Refresh (Entry and Exit)
15. Auto Refresh (CBR)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V5-5/RK 4-0.3/0.3/0.3 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U0986-00 |
| V5-5/RK 4-1/1/1 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U-16415 |
| V5509 | 制造商:Assmann Electronics Inc 功能描述:Old Part V5509^ASSMANN |
| V550-A20 | 制造商:Omron Electronic Components LLC 功能描述:Bar Code Reader, Bcr With Standard Optics |
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