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參數(shù)資料
| 型號： | V54C365804VCT8L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 6/54頁 |
| 文件大?。?/td> | 453K |
| 代理商： | V54C365804VCT8L |
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14
V54C365804VC Rev. 0.6 September 1999
MOSEL VITELIC
V54C365804VC
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1.
4.
If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5.
If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
1.4V
tCS
tCH
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
tT
Figure 1.
tCK
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| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
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| V5-5/RK 4-1/1/1 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U-16415 |
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