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參數(shù)資料
| 型號： | UPD9611GT |
| 廠商： | NEC Corp. |
| 元件分類： | Codec |
| 英文描述： | FOUR-CHANNEL PCM CODEC |
| 中文描述： | 四通道的PCM編解碼器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 161K |
| 代理商： | UPD9611GT |
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μ
PD9611
6
2. CAUTIONS ON USE
(1) Absolute maximum ratings
Application of voltage or current in excess of the absolute maximum ratings to the
μ
PD9611 may result
in damage due to latch up, etc. Be especially cautions about power supply noise, etc.
(2) Wiring pattern
The design of the ground pattern is extremely important for operating the
μ
PD9611 with high precision.
Connect the analog ground pins (AGND1 to AGND4), digital ground pin (DGND) and substrate ground
pin (SUBGND) close to the IC pins, and connect to a wide analog ground line on the board.
(3) Addition of bypass capacitors for power supply pins
Because the
μ
PD9611 uses many internal high-frequency operational amplifiers, high power supply
impedance can cause instability (such as oscillation) in these internal operational amplifiers. To
suppress such instability and eliminate power supply noise, connect all power supply pins (AV
DD
1 to
AV
DD
4, DV
DD
) close to the IC pins, and put bypass capacitors (C
VDD
= approximately 0.1
μ
F) having
superior high-frequency characteristics very close to the pins.
(4) Addition of bypass capacitors for ACOM pins
The
μ
PD9611 incorporates references voltages for signal sources. Superposing of noise on these
reference voltages may have adverse effects on transmission characteristics, etc. Therefore, connect
the ACOM
OUT
pin and ACOM
IN
pin close to the IC pins, and put bypass capacitors (C
ACOM
= approximately
0.1
μ
F) having superior high-frequency characteristics very close to the pins.
(5) Control or SP
DATA
pin on reset
When inputting the setting data from the SP
DATA
pin after the
μ
PD9611 is reset, first input the following
patterns to reset to 0 the couter used to fetch data from the SP
DATA
pin.
16 clocks or more
1 clocks or more
RST
SP
CLK
SP
SYNC
SP
DATA
After ther RST pin has been set to the high level, input 1 clock or more to the SP
CLK
pin, set the SP
SYNC
pin to the high level and input 16 clocks more to the SP
CLK
pin.
During this operation, the SP
DATA
pin is held at the low level. Afterwards, input the setting data.
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