μPD78F921x ONLY) User’s Manual U16994EJ6V0UD 162 Figure 9-3. Format of A/D Co" />
參數(shù)資料
型號： UPD78F9212CS-CAB-A
廠商： Renesas Electronics America
文件頁數(shù)： 73/175頁
文件大?。?/td> 0K
描述： MCU 8BIT 4KB FLASH 16PIN
標準包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 4KB（4K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-DIP（0.300"，7.62mm）
包裝： 托盤
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
162
Figure 9-3. Format of A/D Converter Mode Register (ADM)
Address: FF80H
After reset: 00H
R/W
Symbol
<7>
6
5
4
3
2
1
<0>
ADM
ADCS
0
FR2
FR1
FR0
0
ADCE
ADCS
A/D conversion operation control
0
Stops conversion operation
1
Note 1
Starts conversion operation
fXP = 8 MHz
fXP = 10 MHz
FR2
FR1
FR0
Reference
Voltage
Range
Note 2
Sampling
Time
Note 3
Conversion
Time
Note 4
Sampling
Time
Note 3
Conversion
Time
Note 4
Sampling
Time
Note 3
Conversion
Time
Note 4
0
VDD
≥
4.5 V
12/fXP
36/fXP
1.5
μs
4.5
μs
1.2
μs
3.6
μs
1
0
VDD
≥
4.0 V
24/fXP
72/fXP
3.0
μs
9.0
μs
2.4
μs
7.2
μs
1
0
96/fXP
144/fXP
12.0
μs
18.0
μs
9.6
μs
14.4
μs
1
0
48/fXP
96/fXP
6.0
μs
12.0
μs
4.8
μs
9.6
μs
0
1
0
48/fXP
72/fXP
6.0
μs
9.0
μs
4.8
μs
7.2
μs
0
1
VDD
≥
2.85 V
24/fXP
48/fXP
3.0
μs
6.0
μs
Setting
prohibited
Note 5
(2.4
μs)
Setting
prohibited
Note 5
(4.8
μs)
1
176/fXP
224/fXP
22.0
μs
28.0
μs
17.6
μs
22.4
μs
0
1
VDD
≥
2.7 V
88/fXP
112/fXP
11.0
μs
14.0
μs
Setting
prohibited
Note 5
(8.8
μs)
Setting
prohibited
Note 5
(11.2
μs)
ADCE
Comparator operation control
Note 6
0
Note 1
Stops operation of comparator
1
Enables operation of comparator
Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware
2. The conversion time refers to the total of the sampling time and the time from successively
comparing with the sampling value until the conversion result is output.
Notes 1. Even when the ADCE = 0 (comparator operation stopped), the A/D conversion operation starts if
the ADCS is set to 1. However, the data of the first conversion is out of the guaranteed-value
range, so ignore it.
2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 3
and 4 below are satisfied.
Example
When VDD
≥ 2.7 V, fXP = 8 MHz
The sampling time is 11.0
μs or more and the A/D conversion time is 14.0 μs or
more and 100
μs or less.
Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
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