參數(shù)資料
型號(hào): UPD78F9212CS-CAB-A
廠商: Renesas Electronics America
文件頁數(shù): 163/175頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH 16PIN
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 托盤
CHAPTER 5 CLOCK GENERATORS
User’s Manual U16994EJ6V0UD
86
(3) External clock input circuit
If external clock input is selected by the option byte, the following is possible.
High-speed operation
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
Figure 5-12. Timing of Default Start by External Clock Input
VDD
(a)
(b)
External clock input
PCC = 02H, PPCC = 02H
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note)
Note Operation stop time is 277
μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
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