![](http://datasheet.mmic.net.cn/Renesas-Electronics-America/UPD78F4225YGC-8BT-A_datasheet_99861/UPD78F4225YGC-8BT-A_25.png)
23
User’s Manual U12697EJ4V1UD
13-7
A/D Conversion Operation by Software Start ...................................................................................
237
13-8
Overall Error ......................................................................................................................................
238
13-9
Quantization Error .............................................................................................................................
238
13-10
Zero-Scale Error ...............................................................................................................................
239
13-11
Full-Scale Error .................................................................................................................................
239
13-12
Integral Linearity Error ......................................................................................................................
240
13-13
Differential Linearity Error .................................................................................................................
240
13-14
Method to Reduce Current Consumption in Standby Mode .............................................................
241
13-15
Handling of Analog Input Pin ............................................................................................................
242
13-16
A/D Conversion End Interrupt Request Generation Timing ..............................................................
243
13-17
Conversion Results Immediately After A/D Conversion Is Started ....................................................
244
13-18
Conversion Result Read Timing (When Conversion Result Is Undefined) .......................................
245
13-19
Conversion Result Read Timing (When Conversion Result Is Normal) ............................................
245
13-20
Example of Capacitor Connection Between VDD0 and AVDD .............................................................
246
13-21
Internal Equivalence Circuit of ANI0 to ANI7 Pins ............................................................................
247
13-22
Example of Circuit When Signal Source Impedance Is High ............................................................
247
14-1
Block Diagram of D/A Converter .......................................................................................................
249
14-2
Format of D/A Converter Mode Registers 0 and 1 (DAM0, DAM1) ..................................................
250
14-3
Buffer Amplifier Insertion Example ....................................................................................................
252
15-1
Serial Interface Example ...................................................................................................................
254
16-1
Switching Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ...................................
256
16-2
Block Diagram in Asynchronous Serial Interface Mode ....................................................................
259
16-3
Format of Asynchronous Serial Interface Mode Registers 1 and 2 (ASIM1, ASIM2) ........................
262
16-4
Format of Asynchronous Serial Interface Status Registers 1 and 2 (ASIS1, ASIS2) ........................
263
16-5
Format of Baud Rate Generator Control Registers 1 and 2 (BRGC1, BRGC2) ...............................
264
16-6
Baud Rate Allowable Error Considering Sampling Errors (When k = 0) ...........................................
272
16-7
Format of Asynchronous Serial Interface Transmit/Receive Data ....................................................
273
16-8
Asynchronous Serial Interface Transmit Completion Interrupt Request Timing ................................
275
16-9
Asynchronous Serial Interface Receive Completion Interrupt Request Timing ................................
276
16-10
Receive Error Timing ........................................................................................................................
277
16-11
Block Diagram in 3-Wire Serial I/O Mode .........................................................................................
280
16-12
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
281
16-13
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
282
16-14
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
283
16-15
3-Wire Serial I/O Mode Timing ..........................................................................................................
284
17-1
Block Diagram of Clocked Serial Interface (in 3-Wire Serial I/O Mode) ............................................
286
17-2
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
287
17-3
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
289
17-4
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
290
LIST OF FIGURES (4/8)
Figure No.
Title
Page