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22
User’s Manual U12697EJ4V1UD
8-28
Timing of One-Shot Pulse Output Operation by External Trigger (with Rising Edge Specified) .......
175
8-29
Start Timing of 16-Bit Timer Counter 0 ..............................................................................................
176
8-30
Timing After Changing Compare Register During Timer Count Operation .......................................
176
8-31
Data Hold Timing of Capture Register ..............................................................................................
177
8-32
Operation Timing of OVF0 Flag ........................................................................................................
178
9-1
Block Diagram of 8-Bit Timer/Event Counters 1 and 2 .....................................................................
181
9-2
Format of 8-Bit Timer Mode Control Register 1 (TMC1) ...................................................................
185
9-3
Format of 8-Bit Timer Mode Control Register 2 (TMC2) ...................................................................
186
9-4
Format of Prescaler Mode Register 1 (PRM1) ..................................................................................
187
9-5
Format of Prescaler Mode Register 2 (PRM2) ..................................................................................
188
9-6
Timing of Interval Timer Operation ....................................................................................................
190
9-7
Timing of External Event Counter Operation (with Rising Edge Is Specified) ..................................
193
9-8
Timing of PWM Output ......................................................................................................................
196
9-9
Timing of Operation Based on CRn0 Transitions ..............................................................................
197
9-10
Cascade Connection Mode with 16-Bit Resolution ...........................................................................
198
9-11
Start Timing of 8-Bit Timer Counter ...................................................................................................
199
9-12
Timing After Compare Register Changes During Timer Counting ....................................................
199
10-1
Block Diagram of 8-Bit Timers 5 and 6 .............................................................................................
201
10-2
Format of 8-Bit Timer Mode Control Register 5 (TMC5) ...................................................................
204
10-3
Format of 8-Bit Timer Mode Control Register 6 (TMC6) ...................................................................
205
10-4
Format of Prescaler Mode Register 5 (PRM5) ..................................................................................
206
10-5
Format of Prescaler Mode Register 6 (PRM6) ..................................................................................
207
10-6
Timing of Interval Timer Operation ....................................................................................................
209
10-7
Timing of Operation Based on CRn0 Transitions ..............................................................................
212
10-8
Cascade Connection Mode with 16-Bit Resolution ...........................................................................
213
10-9
Start Timing of 8-Bit Timer Counter ...................................................................................................
214
10-10
Timing After Compare Register Changes During Timer Counting ....................................................
214
11-1
Block Diagram of Watch Timer .........................................................................................................
216
11-2
Format of Watch Timer Mode Control Register (WTM) ....................................................................
218
11-3
Operation Timing of Watch Timer/Interval Timer ...............................................................................
220
12-1
Block Diagram of Watchdog Timer ...................................................................................................
221
12-2
Format of Watchdog Timer Mode Register (WDM) ...........................................................................
223
13-1
Block Diagram of A/D Converter .......................................................................................................
227
13-2
Format of A/D Converter Mode Register (ADM) ...............................................................................
230
13-3
Format of A/D Converter Input Selection Register (ADIS) ................................................................
231
13-4
Basic Operations of A/D Converter ...................................................................................................
233
13-5
Relationship Between Analog Input Voltage and A/D Conversion Result .........................................
234
13-6
A/D Conversion Operation by Hardware Start (When Falling Edge Is Specified) .............................
236
LIST OF FIGURES (3/8)
Figure No.
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