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CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U16890EJ1V0UD
830
CSIA Timing
(1) Master mode
(T
A
=
40 to +125
°
C, V
DD
= EV
DD
= AV
REF0
= 3.5 to 5.5 V, 3.5 V
≤
BV
DD
≤
V
DD
, 3.5 V
≤
AV
REF1
≤
V
DD
, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
REGC = V
DD
= 4.0 to 5.5 V
500
ns
SCKAn cycle time
t
KCY3
<99>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
1000
ns
SCKAn high-/low-level width
t
KH3
,
t
KL3
<100>
t
KCY3
/2
30
ns
REGC = V
DD
= 4.0 to 5.5 V
39
ns
SIAn setup time (to SCKAn
↑
)
t
SIK3
<101>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
68
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
SIAn hold time (from SCKAn
↑
)
t
KSI3
<102>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
60
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
Delay time from SCKAn
↓
to SOAn
output
t
KSO3
<103>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
60
ns
Remark
n = 0, 1
(2) Slave mode
(T
A
=
40 to +125
°
C, V
DD
= EV
DD
= AV
REF0
= 3.5 to 5.5 V, 3.5 V
≤
BV
DD
≤
V
DD
, 3.5 V
≤
AV
REF1
≤
V
DD
, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
REGC = V
DD
= 4.0 to 5.5 V
840
ns
SCKAn cycle time
t
KCY4
<99>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
1700
ns
SCKAn high-/low-level width
t
KH4
, t
KL4
<100>
t
KCY4
/2
30
ns
REGC = V
DD
= 4.0 to 5.5 V
50
ns
SIAn setup time (to SCKAn
↑
)
t
SIK4
<101>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
100
ns
REGC = V
DD
= 4.0 to 5.5 V
50
ns
SIAn hold time (from SCKAn
↑
)
t
KSI4
<102>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
100
ns
REGC = V
DD
= 4.0 to 5.5 V
t
CY
×
2
+
30
Note
ns
Delay time from SCKAn
↓
to SOAn
output
t
KSO4
<103>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 3.5 to 5.5 V
t
CY
×
2
+
60
Note
ns
Note
t
CY
: Internal clock output cycle
f
XX
(CSISn.CKSAn1, CSISn.CKSAn0 bits = 00), f
XX
/2 (CKSAn1, CKSAn0 bits = 01)
f
XX
/2
Remark
n = 0, 1
2
(CKSAn1, CKSAn0 bits = 10), f
XX
/2
3
(CKSAn1, CKSAn0 bits = 11)