參數(shù)資料
型號(hào)： UPD44164362BF5-E40-EQ3-A
元件分類： SRAM
英文描述： 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁(yè)數(shù)： 30/33頁(yè)
文件大小： 494K
代理商： UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 6 of 32
Dec 13, 2010
(2/2)
Symbol
Type
Description
CQ, CQ#
Output
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
ZQ
Input
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground.
The output impedance can be
minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND
or left unconnected. The output impedance is adjusted every 20
μs upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the
new output impedance is reset by implementing power-on sequence.
DLL#
Input
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 k
Ω or less resistor.
TMS
TDI
Input
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
TCK
Input
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
TDO
Output
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
VREF
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
VDD
Supply
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics
for range.
VDDQ
Supply
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See Recommended DC Operating Conditions and DC Characteristics for range.
VSS
Supply
Power Supply: Ground
NC
No Connect: These signals are not connected internally.
相關(guān)PDF資料
PDF描述
UPD442000AGU-DD10X-9JH Circular Connector; No. of Contacts:6; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-98 RoHS Compliant: No
UPD442000AGU-DD12X-9JH Circular Connector; No. of Contacts:22; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:13-35 RoHS Compliant: No
UPD442000AGU-DD85X-9JH Circular Connector; No. of Contacts:10; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:13-98 RoHS Compliant: No
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD44164362F5-E60-EQ1ES 制造商:NEC Electronics Corporation 功能描述:
UPD44165092BF5-E40-EQ3-A 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays
UPD44165094BF5-E40-EQ3-A 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA
UPD44165362BF5-E40-EQ3 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays
UPD44165362BF5-E40-EQ3-A 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA
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