參數(shù)資料
型號: UPD44164362BF5-E40-EQ3-A
元件分類: SRAM
英文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁數(shù): 28/33頁
文件大?。?/td> 494K
代理商: UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 4 of 32
Dec 13, 2010
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μPD44164362B-A]
512K x 36
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/144M NC/36M
R, W#
BW2#
K#
BW1#
LD#
A
VSS/72M
CQ
B
NC
DQ27
DQ18
A
BW3#
K
BW0#
A
NC
DQ8
C
NC
DQ28
VSS
A
A0
A
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
NC
DQ16
E
NC
DQ20
VDDQ
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ14
H
DLL#
VREF
VDDQ
VDD
VSS
VDD
VDDQVDDQ
VREF
ZQ
J
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VDDQ
NC
DQ2
M
NC
DQ34
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
A
VSS
NC
DQ10
P
NC
DQ26
A
C
A
NC
DQ9
DQ0
R
TDO
TCK
A
C#
A
TMS
TDI
A0, A
: Address inputs
TMS
: IEEE 1149.1 Test input
DQ0 to DQ35
: Data inputs / outputs
TDI
: IEEE 1149.1 Test input
LD#
: Synchronous load
TCK
: IEEE 1149.1 Clock input
R, W#
: Read Write input
TDO
: IEEE 1149.1 Test output
BW0# to BW3#
: Byte Write data select
VREF
: HSTL input reference input
K, K#
: Input clock
VDD
: Power Supply
C, C#
: Output clock
VDDQ
: Power Supply
CQ, CQ#
: Echo clock
VSS
: Ground
ZQ
: Output impedance matching
NC
: No connection
DLL#
: PLL disable
NC/xxM
: Expansion address for xxMb
Remarks 1.
×××# indicates active LOW.
2.
Refer to Package Drawing for the index mark.
3.
2A, 3A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
2A and 10A of this product can also be used as NC.
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