參數(shù)資料
型號(hào): UPD44164362BF5-E40-EQ3-A
元件分類: SRAM
英文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁(yè)數(shù): 23/33頁(yè)
文件大?。?/td> 494K
代理商: UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 3 of 32
Dec 13, 2010
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μPD44164182B-A]
1M x 18
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/72M
A
R, W#
BW1#
K#
NC/144M
LD#
A
VSS/36M
CQ
B
NC
DQ9
NC
A
NC/288M
K
BW0#
A
NC
DQ8
C
NC
VSS
A
A0
A
VSS
NC
DQ7
NC
D
NC
DQ10
VSS
NC
E
NC
DQ11
VDDQ
VSS
VDDQ
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ5
G
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
H
DLL#
VREF
VDDQ
VDD
VSS
VDD
VDDQVDDQ
VREF
ZQ
J
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VDDQ
NC
DQ2
M
NC
VSS
NC
DQ1
NC
N
NC
DQ16
VSS
A
VSS
NC
P
NC
DQ17
A
C
A
NC
DQ0
R
TDO
TCK
A
C#
A
TMS
TDI
A0, A
: Address inputs
TMS
: IEEE 1149.1 Test input
DQ0 to DQ17
: Data inputs / outputs
TDI
: IEEE 1149.1 Test input
LD#
: Synchronous load
TCK
: IEEE 1149.1 Clock input
R, W#
: Read Write input
TDO
: IEEE 1149.1 Test output
BW0#, BW1#
: Byte Write data select
VREF
: HSTL input reference input
K, K#
: Input clock
VDD
: Power Supply
C, C#
: Output clock
VDDQ
: Power Supply
CQ, CQ#
: Echo clock
VSS
: Ground
ZQ
: Output impedance matching
NC
: No connection
DLL#
: PLL disable
NC/xxM
: Expansion address for xxMb
Remarks 1.
×××# indicates active LOW.
2.
Refer to Package Drawing for the index mark.
3.
2A, 7A, 10A and 5B are expansion addresses
: 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
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