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參數(shù)資料
| 型號： | UPD44164362BF5-E40-EQ3-A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 29/33頁 |
| 文件大?。?/td> | 494K |
| 代理商： | UPD44164362BF5-E40-EQ3-A |
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μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 5 of 32
Dec 13, 2010
Pin Description
(1/2)
Symbol
Type
Description
A0
A
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. All transactions operate on a burst of two
words (one clock period of bus activity). A0 is used as the lowest order address bit
permitting a random starting address within the burst operation on x18 and x36
devices. These inputs are ignored when device is deselected, i.e., NOP (LD# =
HIGH).
DQ0 to DQxx
Input/Output
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data
clocks or to K and K# if C and C# are tied to HIGH.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
LD#
Input
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data (one clock period of bus activity).
R, W#
Input
Synchronous Read/Write Input: When LD# is LOW, this input designates the access
type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded
address. R, W# must meet the setup and hold times around the rising edge of K.
BWx#
Input
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. See Pin Configurations for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
K, K#
Input
Input Clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges.
C, C#
Input
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally,
C# is 180 degrees out of phase with C. When use of K and K# as the reference
instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed
unless C and C# are fixed to HIGH (i.e. toggle of C and C#)
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44165362BF5-E40-EQ3 | 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays |
| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
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