
Data Sheet U16277EJ1V0DS
28
μ
PD30181A, 30181AY
(3/7)
Pin Name
(Signal Name)
Alternate-
Function Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
CF1_CD(2:1)#
FPD(11:10),
GPIO(47:46)
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_CE(2:1)#
FPD(13:12) ,
GPIO(49:48)
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_STSCHG#
FPD14, GPIO50
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_READY
FPD15, GPIO51
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_RESET
DBUS32
Note 2
Hi-Z
Hi-Z
Note 1
Note 3
CF1_DIR
KPORT4,
GPIO39
Hi-Z
Hi-Z
0
Note 1
Hi-Z
CF1_EN#
KPORT5,
GPIO38
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_VCCEN#
KSCAN4,
GPIO37
Hi-Z
Hi-Z
1
Note 1
Hi-Z
CF0_CD(2:1)#
GPIO(36:35)
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_IOIS16#
GPIO34
Hi-Z
Hi-Z
–
–
Hi-Z
CF_WAIT#
GPIO33
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_CE(2:1)#
GPIO(32:31)
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_STSCHG#
GPIO30
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_READY
GPIO29
Hi-Z
Hi-Z
–
–
–
CF0_RESET
GPIO28
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_DIR
GPIO27
Hi-Z
Hi-Z
0
Note 1
Hi-Z
CF0_EN#
GPIO26
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF_REG#
GPIO25
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_VCCEN#
GPIO24
Hi-Z
Hi-Z
1
Note 1
Hi-Z
CLK48
–
Hi-Z
Hi-Z
Note 3
Note 3
Hi-Z
UHDP
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UHDN
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UPON
–
0
0
0
0
0
UOC
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UDP
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Notes 1.
The status in the previous Fullspeed mode is retained.
2.
The input level is sampled when the RTCRST# signal has changed to high level in order to set the
boot ROM bus width.
3.
The registers in the GIU can be used to set 1, 0, or high impedance.
Remarks 1.
0: Low level, 1: High level, Hi-Z: High impedance
2.
When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.