參數資料
型號： UPD30181AYF1-131-GA3-A
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數： 13/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3-A
Data Sheet U16277EJ1V0DS
13
μ
PD30181A, 30181AY
(2) Memory interface signals
Signal Name
I/O
Function
Alternate Function
SDCLK
O
Operating clock for SDRAM and SyncFlash memory
This signal can also be set (via register settings) to stop clock output
when not accessing SDRAM or SyncFlash memory.
–
CKE1
O
Operating clock enable signal for SyncFlash memory
A24
CKE0
O
Operating clock enable signal for SDRAM
–
SDCS(3:2)#
O
Chip select signal for SyncFlash memory
–
SDCS(1:0)#
O
Chip select signal for SDRAM
–
RAS#
O
Row address strobe signal for SDRAM and SyncFlash memory
–
CAS#
O
Column address strobe signal for SDRAM and SyncFlash memory
–
DQM(3:0)
O
Byte enable signal for SDRAM and SyncFlash memory
The DQM(3:0) signals for SDRAM and SyncFlash memory shares pins
with the LBE(3:0)# signals for 32-bit general-purpose devices, so the
function of these pins change based on time division. When the SYSEN#
signal is at high level, the pin operates as the DQM(3:0) signals which are
referenced by SDRAM.
LBE(3:0)#
WE#
O
Write enable signal for SDRAM and SyncFlash memory
–
RP#
O
SyncFlash memory initialization/power down signal
A23
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