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參數(shù)資料
| 型號： | UPD16879 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 199K |
| 代理商： | UPD16879 |
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Data Sheet S14188EJ1V0DS00
3
μ
PD16879
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, T
A
= 25
°
C, V
DD
= 3 V, V
M
= 5.4 V, f
CLK
= 4.5 MHz, C
OSC
= 68 pF, C
FIL
= 1000 pF,
V
REF
= 250 mV, EVR = 100 mV (10000))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Off state V
M
pin current
I
MO(RESET)
No load, Reset period
1.0
μ
A
Operating state V
DD
pin current
I
DD
Output open
3.0
mA
V
DD
pin current
I
DD(RESET)
Reset period
100
μ
A
I
DD(PS)1
t
CLK
= off
100
μ
A
Power save state V
DD
pin current
I
DD(PS)2
f
CLK
= 4.5 MHZ
300
μ
A
High level input voltage
V
IH
0.7
×
V
DD
V
Low level input voltage
V
IL
0.3
×
V
DD
V
Input hysteresis vosltage
V
H
LATCH, SCLK, SDATA, V
D
, V
D
RESET, OSC
IN
, V
REFsel
0.3
V
V
OM
α
(H)
V
OM
β
(H)
0.9
×
V
DD
V
Monitor output voltage 1
(EXTOUT
α
,
β
)
V
OM
α
(L)
V
OM
β
(L)
4th byte
0.3
0.1
×
V
DD
V
V
OEXP(H)
Pull up (V
DD
)
0.9
×
V
DD
V
Monitor output voltage 2
(EXP 0,1 open drain)
V
OEXP(L)
I
OEXP
= 100
μ
A
0.1
×
V
DD
V
High level input current
I
IH
V
IN
= V
DD
1.0
μ
A
Low level input current
I
IL
V
IN
= 0
1.0
μ
A
Reset pin high level input current
I
IH(RST)
V
RST
= V
DD
1.0
μ
A
Reset pin low level input current
I
IL(RST)
V
RST
= 0
1.0
μ
A
H bridge ON resistance
R
ON
I
M
= 100 mA, upper + lower
6.0
Chopping frequency
Note 1
f
OSC
Refer to table 1 (TYP.)
kHz
Internal reference voltage
V
REF
225
250
275
mV
V
D
delay time
Note 2
t
VD
250
ns
Sin wave peak output current
(reference value)
Note 3
I
M
L = 15 mH/R = 70
( 1 kHz)
R
S
= 6.8
, f
OSC
= 72.58 kHz
EVR = 220 mV (11100)
53
mA
FIL pin voltage
Note 4
V
EVR
EVR = 200 mV (11010)
V
REF
= 250 mV external input
370
400
430
mV
FIL pin step voltage
Note 4
V
EVRSTEP
Minimum step
20
mV
H bridge turn on time
Note 5
t
ONH
2.0
μ
s
H bridge turn off time
Note 5
t
OFFH
I
M
= 100 mA
2.0
μ
s
Notes 1.
When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur.
When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation.
2.
By OSC
IN
and V
D
sync circuit
3.
FB pin is monitored.
4.
FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.
5.
10% to 90% of the pulse peak value without filter capacitor (C
FIL
)
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