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參數(shù)資料
| 型號： | UPD16879 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 199K |
| 代理商： | UPD16879 |
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Data Sheet S14188EJ1V0DS00
21
μ
PD16879
Enable sets by D7 bit.
D7 bit data is “0”: Output high impedance (but, internal counter increase)
D7 bit data is “1”: Output conducts
Rotation sets by D6 bit.
D6 bit data is “0”: Forward turn (CW mode)
D6 bit data is “1”: Reverse turn (CCW mode)
Output current sets by D0 to D4 bits.
The 250 mV (typical) voltage input from external source or internal reference voltage is internally doubled and
input to a 5-bit D/A converter. By dividing this voltage by 5-bit data, a current setting reference voltage can be set
inside the IC within the range of 100 to 500 mV, in units of 20 mV. If external source is used, the V
REFsel
pin connects
V
DD
pin. If internal reference voltage is used, the V
REFsel
pin and V
REF
pin connect GND pin. The 64 steps micro-step
(setting reference voltage is maximum) control is possible.
Table 9. Output Current Setting Reference Voltage Data (
α
channel data)
EVR setting
D4
D3
D2
D1
D0
FIL pin voltage
EVR setting
D4
D3
D2
D1
D0
FIL pin voltage
50 mV
0
1
0
1
1
100 mV
160 mV
1
0
1
1
0
320 mV
60 mV
0
1
1
0
0
120 mV
170 mV
1
0
1
1
1
340 mV
70 mV
0
1
1
0
1
140 mV
180 mV
1
1
0
0
0
360 mV
80 mV
0
1
1
1
0
160 mV
190 mV
1
1
0
0
1
380 mV
90 mV
0
1
1
1
1
180 mV
200 mV
1
1
0
1
0
400 mV
100 mV
1
0
0
0
0
200 mV
210 mV
1
1
0
1
1
420 mV
110 mV
1
0
0
0
1
220 mV
220 mV
1
1
1
0
0
440 mV
120 mV
1
0
0
1
0
240 mV
230 mV
1
1
1
0
1
460 mV
130 mV
1
0
0
1
1
260 mV
240 mV
1
1
1
1
0
480 mV
140 mV
1
0
1
0
0
280 mV
250 mV
1
1
1
1
1
500 mV
150 mV
1
0
1
0
1
300 mV
Remark
If D0 to D4 bits input “00000” to “01010”, EVR value fixed 50 mV (FIL pin voltage fixed 100 mV).
FIL pin (peak voltage) is output about double of EVR setting value.
[6th byte]
The 6th byte sets pulse number during 1V
D
period of
α
channel. The pulse number setting 1020 pulses maximum.
It is set by eight bits in terms of software. However, the actual circuit uses 10-bit counter with the low-order two bits
fixed to “0”. Therefore, the number of pulses that is actually generated during fall edge of the first point wait time +
first point magnetize wait time (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a
range of 0 to 1020 and in units of four pulses.
Table 10. 6th Byte Data Configuration (
α
channel data)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
Pulse number/V
D
Data
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
00000000
0
MSB
LSB
00000001
4
11111111
1020
n
n
×
4
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