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參數(shù)資料
| 型號(hào)： | UPD16878 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 242K |
| 代理商： | UPD16878 |
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Data Sheet S15974EJ1V0DS
19
μ
PD16878
(Data Update Timing)
The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product
are set and updated at the following latch timing.
Table 5-14. Data Update Timing
ENABLE change
1
→
1
0
→
1
1
→
0
0
→
0
Pulse width
FF2
↓
FF2
↓
FF2
↓
Number of pulses
FF2
↓
FF2
↓
FF2
↓
Rotation direction
FF2
↓
FF2
↓
FF2
↓
Current setting
FF2
↓
FF1
↓
FF2
↓
ENABLE
FF2
↓
FF1
↓
FF2
↓
The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status.
For example, suppose the enable signal is currently
“
0
”
(output high impedance) and
“
1
”
(output conduction) is
input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at
FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon
completion of start up drive wait).
V
D
FF1
Start up wait
FF2
Start up wait +
start up drive wait
Pulse output
V
D
LATCH
I1
Pulse width, number of pulses, and rotation direction
are updated.
Current setting and ENABLE are updated
(ENABLE change: 0 to 1).
Initial data
identification
(1)
S1
(2)
S2
(3)
S3
Standard data
identification
I1 data is output.
FF1, FF2 output
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